AM35x Schematic Checklist

Content is no longer maintained and is being kept for reference only!

Introduction

This page applies to the following devices:

• AM3517
• AM3505

Here are some links to schematics you can refer to:

AM35x SOM (System on Module) from LogicPD
Craneboard open source design

Recommendations Specific to AM35x

Critical Connections

Power

• If using TPS659xx devices, please refer to the following app notes for more information on schematic and layout recommendations:
  • SWCA073
  • SWCA076
  • SWCU056
  • SWCU055

• Check decoupling capacitors (refer to the appropriate Data Manual for your device). Recommend 1 capacitor per 2 to 4 balls.
• VPP : should be left unconnected for production
• If using TPS6595x PMIC, SYS_CLKREQ should be connected to TPS6595x CLKREQ. SYS_CLKREQ signal polarity is programmable using PRM_POLCTRL register, so ensure your external hardware matches the intended use of this signal.

• If using TPS65023, refer to the TPS65023 Design-In Wiki
• If using TPS65073, refer to the TPS65073 Design-In Wiki
• If using TPS65910, refer to the TPS65910 Product Folder

RESETS

-Need to add an open-drain buffer to warm reset. (Please see AM35x EVM schematics for an example). Also, ensure you put an 4.7K pullup (at the output of the buffer) Here is the reason for the buffer:

1. SYS_NRESWARM is pulled-low when SYS_NRESPWRON is LOW.
2. Once SYS_NRESPWRON goes HIGH, for PRM_RSTTIME, SYS_NRESWARM will be driven LOW (No pull down).
3. After that SYS_NRESWARM will be pulled high internally.

On the EVM, the initial pull down from AM3517 is fighting with the internal pull up on the 8710 (Ethernet PHY), causing a voltage divider. In most cases, the LAN8710 was actually seeing a high voltage, meaning it was out of reset and trying to link at 100Mbit full duplex. Upon SYS_NRESPWRON going high, the 8710 would see another low then high on the its reset. This pulse actually ends up being too short, and the 8710 would drop back into 10Mbit half duplex mode.

The buffer was put in there to ensure the reset to the LAN8710 (and to other devices) would be driven low the entire SYS_NRESPWRON time + PRM_RSTTIME. This also allows the mode pins on the Ethernet PHY to be latched properly on reset.

• Typically, warm reset is used for a push button reset or reset from external circuits. However, be aware that warm reset does not follow the same boot up sequence that a power on reset performs. If you want a reset that will be following by the boot order you establish for power on reset, you must use SYS_NRESPWRON.

Clocks

• For the High Frequency clock, AM3505/17 can only support 26MHz crystal or oscillator input.
• 26MHz oscillator must be 50ppm or less.
• The 32KHz clock can be obtained externally (connect a 32KHz oscillator), or can be derived from the 26MHz clock if you want to reduce the BOM cost of a 32KHz oscillator. Note that the internally generated 32K is not accurate (~32.5K), so it cannot be used as a accurate source for internal timers.
• ensure that the startup time for both oscillators is shorter than the SYS_NRESPWRON delay time. Both clocks must be stable before SYS_NRESPWRON is released.
• When using a 26MHz crystal for the high frequency clock, connect the crystal case ground and associated load caps to VSSOSC only (not to board ground). Also add option to connect to board ground through 0 ohm resistor. This will give you the option to connect to board ground at one point if needed.

Pin States

• Check reset states of AM35x pins connected to other devices. AM35x pins may have inadvertent states at or right after reset which may conflict with external devices. This information can be found in the AM35x Data Manual "Ball Characteristics" table. Check the columns Ball Reset State, Ball Reset Rel. State, and Reset Rel. Mode.

Booting

• Note that if you are looking to boot from UART, only UART3 can be used for booting (You cannot boot from UART1 or UART2). Also, UART3 is used for terminal debug. It is recommended that you connect a transceiver to this port (check EVM schematics for reference)
• For normal operation Please ensure sys_boot8 pin is pulled down.

Layout Guidelines

These are generic layout guidelines for BGA packaging:
BGA PCB Design Guidelines
BGA Decoupling Capacitor Guidelines

Peripherals

I2C

• Pull ups on SDA and SCL. 4.7K can be used. When implementing high speed I2C, lower values (470ohm) should be used.

GPIO

• The following GPIOs are input only: GPIO99,100,112,113,114. All other GPIOs are IOs.

MMC interface

• MMC_CLK : no pull ups needed
• MMC_CMD, MMC_DATx : 10K pull ups needed on each signal, unless using it in SDIO mode (eg., connected to a WLAN device) . Be sure to pull up to MMC voltage (VDDSHV).
• MMC1_CLK, MMC2_CLK and MMC3_CLK, series resistor is needed, place as close to AM35x as possible. Recommended value is 33ohm, but will need to be adjusted based on trace length to the MMC peripheral.
• If using MMCx_WP (write protect) and MMCx_CD (card detect) signals, they would typically be pulled up to VDDSHV before connecting to the processor GPIO.

TV OUT interface

Refer to the TV out Application note. This app note is applicable to AM35x family of devices.

• Note that inductors on TVout circuit should be 3.3uH. Some AM35x schematics have them as 3.9nH, which is a typo.

DSS

• refer to the Display Subsystem wiki for guidance on connecting the DSS.
• add 10ohm series resistors to all data lines, HSYNC, VSYNC, ACBIAS, PCLK
• Remember that AM3505/17 does not have data lane shifter like OMAP35x and if 8 bit YCbCr data is used you would need to shift 8 bits up to 8 MSBs. Only way to get 8 bit data piped through is by using Alaw compression which caused CbCr offset resulting in a greenish tint issue with TVP5146 8 bit data on AM35x EVM. The following wiki article explains the change needed on the EVM: Errata

GPMC

• check to make sure any pullups for WAIT signals are pulled up to VDDSHV.
• if used, ensure GPMC_CLK has 33ohm series resistor placed close to AM35x

McBSP

• Some McBSPs have different sized internal FIFOs. McBSP2 has 5K FIFO (others have only 512 bytes).
• McBSP2 and McBSP3 have sidetone capabilities.
• Place 33ohm series resistor close to AM35x on all McBSP clock signals

USB OTG

• for OTG operation, USB VBUS decoupling capacitance should be 1-6.5uF
• for device operation, USB VBUS decoupling capacitance should be < 10uF. Leave USB0_DRVVBUS and USB0_ID as no connect.
• for host operation, USB VBUS decoupling capacitance should be > 120uF
• ensure the VBUS decoupling capaciance is connected close to USB connector.
• ID signals should not be pulled down with a pull down resistor. If defaulting to an A-device, ground the ID signal on the USB PHY.
• ensure VBUS from the USB connector is connected to AM35x USB0_VBUS signal. Additionally, a charge pump or other power source needs to be connected to VBUS intending to use USB host mode, as it would need to provide proper power to downstream peripherals.

USB Host ports (HSUSB1 - HSUSB3)

• HSUSB3 will only support FS/LS USB PHYs.
• Review the Errata for issues concerning USB Host ports.
• For USB Host ports (USB1 and USB2), we recommend using TI's TUSB1210 USB PHY. This PHY supports input clocking mode (ie, the PHY is in slave mode and OMAP35x sources the 60MHz ULPI clock). This device has recently been released.
• It is not recommended to use the SMSC3320 if you are planning to use the USB suspend feature due to an specific interoperability errata with this device (refer to the AM35x errata). If using a SMSC332x PHY, it is recommended to supply the 1.8V to the PHY with a separate low noise power source.
• The TUSB1210 and SMSC3320 are pin-for-pin compatible, with some minor modifications. If you want to design your board to accomodate both, please see the following schematic, which details the changes that need to be made to the OMAP3EVM to change from the SMSC332x to the TUSB1210.

DDR2

• ensure that you follow the recommended layout guidelines and series termination values in section 6.4.2 of the AM35x Data Manual. Termination on AM35x outputs should be close to AM35x. Termination on Bi-Directionals should be close to memory. Ensure termination across net classes are the same value.
• ensure the resistor divider circuit for VREF contains 1% precision resistors
• ensure the resistor for DDR_PADREF is 50ohm / 1% precision

Ethernet

• RMII requires 50ppm crystal
• 1.5K pullup is recommended on RMII_MDIO_DATA
• The AM35x EVM uses SMSC LAN8710 for the Ethernet PHY. Although the LAN8720 looks to be a better option, as it is RMII only (AM35x only supports RMII), and it only needs a 25MHz crystal (usually cheaper than a 50MHz oscillator), we do not recommend this device as it operates outside the RMII spec, and will violate timing relative to AM35x. Check the SMSC website for more details.
• Ethernet TXP/TXN/RXP/RXN lines should be routed as 100 ohm differential pairs with matched trace lines.
• Ensure minimal stubs when adding resistors or capacitors off of TXP/TXN/RXP/RXN signals.
• If your system requires ethernet boot, ensure that the Ethernet PHY is initialized properly (ie, it is out of reset and clock is stable) before the AM35x ROM code executes (ie, before SYS_PWRONRST deasserts). The ROM expects the PHY to be ready because it sends out a broadcast packet to initiate the ethernet boot. If the PHY isn't ready, it won't send out the packet and the ethernet boot will fail. One recommendation is to delay the reset signal going to SYS_NRESPWRON with some sort of RC circuit or buffer, long enough to for the PHY to come out of reset and initialize (this time should be specified in the PHY datasheet). If you need to separately reset the PHY during normal operation, you can add an AND gate to add control from an AM35x GPIO.
• when configuring the mode bits on the ethernet PHY, ensure that those signals will be in the correct state when the PHY reset is deasserted (this is when they are typically latched). Check the reset state and reset release state in the AM35x datasheet for these signals to ensure external pull up/downs do not conflict with the state of these signals before and after SYS_PWRONRST. Typical pull up/down drive strengths are 100uA.

McSPI

• place series resistor close to AM35x on all MCSPI clock signals.

If not used

What to do with unused Power signals

• VDDA_DAC: if signals powered by VDDA_VDAC are not used, tie to ground.

• VDDA3P3V_USBPHY: if USB0 OTG is not being used, tie to ground.
• VDDA1P8V_USBPHY: if USB0 OTG is not being used, connect to 1.8V supply.
• CAP_VDDA1P2LDO_USBPHY: if USB0 OTG is not being used, a cap is not required. Keep the pin floating. Don’t ground this.

All other power rails should be powered at all times.

TV Output

When the TV output is not required then the following configuration should be implemented in order to reduce the power consumption to its minimum value.

The analog pins tv_vref, vssa_dac, VDDA_DAC, tv_out1/2 and tv_vfb1/2 should be grounded.

To avoid internal current leakage, the following bits must be set to 0: DSS.DSS_CONTROL[5] DAC_POWERDN_BGZ DSS.VENC_OUTPUT_CONTROL[2:0] PRCM.CM_FCLKEN_DSS[2] EN_TV CONTROL.CONTROL_DEVCONF[18] TVOUTBYPASS

General Recommendations

THIS SECTION IS TRANSCLUDED FROM HARDWARE DESIGN CHECKLIST. ONLY INFO GENERIC TO ALL DEVICES BELONGS HERE SINCE IT APPEARS IN ALL SCHEMATIC CHECKLISTS.

As you are creating the schematics for your project here are a few things to consider. Before you begin Documentation Make sure you have the latest version of documentation, especially the data sheet and silicon errata. TIP: Try searching the documentation for words such as: "must", "require", "do not", "shall", "note:", etc. Important criteria for the device will typically contain one or more of these words. This is an easy way to make sure you have not missed anything important. TIP: - on each ti.com device product folder there is a button "Alert me about changes to this product". Registration here will enable proactive automatic notification of device errata. Pin out Have you verified that your pin labels correspond to the correct pin numbers? Have you verified that the power pins are connected to the correct supply rails? Pullups/Pulldowns: Internal pull-up/pull-down resistors are implemented with weak transistors. As the voltage present on the I/O pin varies the relative gate voltage to this weak transistor changes which will cause the effective pull-up/pull-down resistance to change. Therefore, internal resistors do not have a linear response like external resistors. The non-linearity along with process voltage and temperature variations require internal pull-up/pull-down resistors to be specified with a wide range of resistance or current sourcing/sinking. The input current without a pull-up or pull-down turned on defines the input leakage without any current from internal pull resistors. The input current with a pull-up or pull-down turned on defines a combination of input leakage current and current required to force the internal pull resistors to the opposite voltage rail. For example, if an internal pull-up is turned on the value shown represents the total current required to pull the input to VSS. When deciding what value of external resistor to use, you must consider the worst case combination of all internal leakage paths of all devices connected to a signal and make sure the external resistor is able to force these internal leakage paths to a potential greater than Vih min, or less than Vil max. Critical Connections Decoupling Capacitors Voltages from traces on a printed circuit board can couple to each other in places where it is not desired, (like power supply planes). To decouple the traces, we add capacitors to absorb some of the voltage and help reduce this effect. For more information on how to correctly place decoupling caps, see the data sheet section for power-supply decoupling. PLL and some analog supplies benefit from filters or ferrite beads to keep the noise from causing clock jitter. The minimum recommendation is a ferrite bead with a resonance at 100 MHz along with at least one capacitor on the device side of the bead. Additional recommendation is to add one capacitor just before the bead to form a Pi filter. The filter needs to be as close as possible to the device pin, with the device side capacitor being the most important thing to be close to the device pin. PLL pins close together can be combined on the same supply. PLL pins farther away from each other may need their own filtered supply. Refer to General Hardware Design/ BGA PCB Design/BGA Decoupling Wiki Power Sequencing Are all requirements being met in terms of the order, delays, etc. of the power supplies? Clocking Make sure your input clock/crystal meets the data sheet requirements. For example: Frequency ESR for crystal Load capacitance meets both the crystal’s and processor’s requirements Crystal and caps placed physically close to processor Double check proper voltage level for clock (some devices will use core voltage, others I/O voltage). If there are any PLL configuration pins make sure they are set such that the resulting frequency is within device spec. Also, having alternate population options for those PLL pins could be handy. OSC Internal Oscillator Clock source The figure below shows the recommended crystal circuit. It is recommended that pre-production printed circuit board (PCB) designs include the two optional resistors Rbias and Rs. They may be required for proper oscillator operation when combined with production crystal circuit components. OSC Crystal Circuit Schematics In general, adding Rbais and Rs resistors improves circuit performance by reducing the long start-up time, crystal overdrive and voltage and temperature related issues. Specifically, they provide the following functionality: Rs helps reduce the drive level on the crystal and decreases the slew rate, which adds additional phase shift Recommended value: 50 Ohms Rbais (a.k.a. the feedback resistor) is used to bias the input of the inverting amplifier and improve the loop gain Recommended value: 1M Ohms However, in most cases Rbias is not required and Rs is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator performance with production crystal circuit components installed on pre-production PCBs. Please refer the below application note for calculation of Rs and RBais values: Please refer the application note for the calculation of Rs and RBais values Crystek Application notes Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the OMAPL1x package. Parasitic capacitance to the printed circuit board (PCB) ground and other signals should be minimized to reduce noise coupled into the oscillator. Reset Make sure that reset is kept asserted for the processor as the power supplies are ramping. You must not release the processor from reset until all the proper voltage/clocking is in place as specified by the data sheet. Conversely make sure that something on the board is actually RELEASING the reset once power and clocks are stable! A useful tip is to place a 0.1uF cap near the reset pin to help avoid ESD-induced resets. Also, you might want to have a reset button on your board as it can be helpful for development. Boot modes Double check that the boot configuration pins are set to the correct option. It's highly recommended to have some population options to be able to easily change the reset mode. This can be handy in a variety of circumstances. For example, if you were doing a NOR flash boot and you ever accidentally put in some bad code you might end up in a scenario where you can't connect to the device with emulator because it's in a bad state, and you can't reprogram the flash as a result! Having an alternate boot mode can be a life saver! Read carefully the initialization section in the Technical Reference Manual of your processor. We may have to deal with important information that can change your design. Look for which chip select is used by default, default clock setups, bus widths, wait states, supported booting devices, initial fetch address and interrupt vector addresses, default memory map and so on. CAUTION: Be careful if anything is hooked up to these pins (i.e. if the pins are have multiple uses such as GPIO or other peripherals). You must make sure that the boot pins are at the proper levels when power-on reset occurs such that the correct values are latched in order for the device to boot correctly! Pin Muxing Although pin muxing is frequently software configurable, often the initial configuration is dependent on several configuration pins (e.g. are they high or low when reset is released). Make sure that the initial pin muxing corresponds properly with your boot modes so that any interfaces necessary for boot will be available. On some devices this could potentially be handled by the boot ROM, but to be certain you should configure the initial pin muxing appropriately. Peripherals USB Check that there are no unnecessary USB_DM or USB_DP connections that would form stubs. Check that there is nothing on the DP/DM lines (except for possibly a USB 2.0 certified surge suppressor) USB supports hot insertion and removal so it is very vulnerable to ESD resulting from this. External ESD protection like the TPD2E001 or TPD3E001 is recommended. For USB OTG the recommended ESD protection is the TPD4S012. Any USB 2.0 certified ESD protection chip is acceptable as long as the USB PCB routing guidelines are followed. DDR2 Routing Checklist DDR2/mDDR Routing Checklist External Memory Interface (NOR/async) The mapping of address pins to the memory interface is a device-specific detail that often depends on the bus width (8- or 16-bit data bus). For example in some devices the upper address bits get mapped down to handle the least significant bit while in other devices the pins may all "shift" depending on the width of the interface. Double check the documentation to verify the address mapping is handled correctly. I2C ~5K pull ups on both lines (only one set, or two sets of 10K pull ups) are recommended Make sure all devices on a given I2C bus have unique addresses (often this is configurable through a pin to enable multiple of the same device) UART This simple peripheral is frequently hooked up incorrectly. Make sure it's connected as follows: TX ---> RX RX <--- TX Debug Considerations JTAG/Emulation This is something often done incorrectly which can severely impact your ability to develop code! Please follow these recommendations when designing your JTAG interface. The XDS Connector Design Checklist provides a convenient list of recommendations per XDS/JTAG signal. You might also want to look at the article JTAG Connectors when deciding which header to put on the board. Double-check the pin-out! Signal Visibility For debugging purposes you may need to look at a signal on an oscilloscope. Therefore you'll want to make sure you can get access to the signals, particularly with BGA devices where it might otherwise be impossible. This can be done by bringing a via all the way through the board or other times where a pullup/pulldown is needed you can probe at the resistor. Having a GPIO brought to a test point or an LED can be useful as well. Other Voltage Level Changes Can you change the supply voltage with some simple resistor changes? Sometimes a pin-for-pin compatible release is made at a higher speed, sometimes requiring higher voltage and so having this flexibility on your board can save you trouble later. Signal Terminations Careful attention should be paid to any notes in the data sheet regarding the correct termination of pins. In particular make sure that termination instructions are exactly followed on reserved pins. Also, there are often pins that have special significance at the time the device reset is released. Often these are documented with something like "do not oppose this pin at reset" meaning that if there is an internal pullup or pulldown on that pin, you should not drive that pin in the opposite direction at reset. This would include not putting an opposing pullup/pulldown and also making sure that anything connected to that pin does not drive the pin opposite the intended direction. For any unused pin you should pay attention to how it is terminated. Frequently pins will default to an input state and if they are left floating they may pick up noise and toggle at a high frequency. This can cause significant unwanted current consumption. Unused pins should be checked to see if they can be configured through software as outputs so they are not floating. If there is an internal pull-up/down you should configure the level of the output (high/low) to match the pull-up/down for lowest current consumption. Ground Symbols The ground symbols must have applicable names assigned to them. Also, the display field must be turned on so that the name of each ground symbol is displayed on the schematic to help in reviews to verify that no ground connections are orphaned by mistake. Use a standard triangle ground symbol for the main digital ground. Then use a signal ground (symbol with decreasing horizontal lines) for all other grounds. Use different names for these local grounds to allow easy review of the schematic as well as easy referral to them in the PCB layout tools. Power Symbols The power symbols must have applicable names assigned to them. Also, the display field must be turned on to show the unique name for each power net. Placing a ‘V’ for the first character of a power supply can ease the schematic verification process since the power supply net names will appear next to each other in the view of the nets on the board. References This article began from spraa34 which was a design checklist for the DM642. It has been generalized a bit to make it more applicable to all designs.