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OMAP35x To AM37x Hardware Migration Guide
Contents
- 1 Abstract
- 2 Software Migration Guide
- 3 Basic Feature comparison
- 4 General migration careabouts
- 5 Feature Enhancements
- 6 Pinmultiplexing updates
- 7 ROM Code updates
- 8 Revision update
- 9 Removed Features
- 10 Errata Fixes
Abstract[edit]
This document describes device considerations to migrate a design based on a TI OMAP3530 Application Processor to one based on a TI AM/DM37x System-on-Chip (Application processor). These two devices are based on similar ARM CPU cores, feature Neon & SGX graphics processor and a mixture of memory and other peripherals useful in a system environment. This document describes the details for performing this migration. Since this document describes migration from OMAP3530 device to AM37x device, familiarity with the OMAP3530 device and its documentation is assumed. Note that all of the documentation referenced in this migration guide can be found on the TI website located in the two device respective product folders. The device folders are found at the following web pages.
Software Migration Guide[edit]
For more information on software migration, please see OMAP35x to AM/DM37x Software Migration guide.
Basic Feature comparison[edit]
The table below shows a comparison of the basic features of the OMAP35xx and the AM/DM37xx. The remainder of this document presents a comparison of these features in greater detail, and also provides references to the appropriate documentation for further information.
| Device Family | AM/DM37x | OMAP35x | |
| Device Family | AM3703 - CortexA8 AM3715 - CortexA8 + SGX 530 DM3725 - CortexA8 + IVA2.2 DM3730 - CortexA8 + IVA2.2 + SGX 530 |
OMAP3503 - CortexA8 OMAP3515 - CortexA8 + SGX 530 OMAP3525 - CortexA8 + IVA2.2 OMAP3530 - CortexA8 + IVA2.2 + SGX 530 | |
| Package Options | |||
| Packages | CBP - 0.4 mm bottom, 0.5 mm top CBC - 0.5 mm bottom, 0.65 mm top CUS - .65 mm bottom. [layout using .8 mm rules] |
CBB - 0.4 mm bottom, 0.5 mm top CBC - 0.5 mm bottom, 0.65 mm top CUS - .65 mm bottom. [layout using .8 mm rules] | |
| Co-processors and Subsystems | |||
| CortexA8 Processor | r3p2; 32k L1 I$ & 32k D$. Cortex-A8 up to 1GHz | r1p7; 16k L1 I$ & 16k D$. Cortex-A8 up to 720MHz | |
| 2D/3D Graphics Accelerator | Increase to 200 MHz | 110 MHz | |
| IVA2.2 Subsystem | Increase to 800 MHz | 520 MHz | |
| Neon Co-processor | Y | Y | |
| System DMA | updated linked list | Y | |
| Memory Interfaces: | |||
| SDRC | |||
| SDRAM Controller | Increase to 200 MHz | 166 MHz | |
| SDRAM Memory Scheduler (SMS) | Y | Y | |
| Rotation Engine | Y | Y | |
| Mobile DDR SDRAM (mDDR) | Y | Y | |
| Width (bits) | 16,32 | 16,32 | |
| GPMC | 128 MB per CS, 1 GB total address space | 128 MB per CS, 1 GB total address space | |
| Chips Selects | Y | Y | |
| Wait Pins | Y | Y | |
| Width (bits) | 8,16 | 8,16 | |
| POP | (CBP & CBC Package) | (CBB & CBC Package) | |
| Discrete memory (LPDDR) Interface (non PoP) | (CUS Package only) | (CBB & CUS Package) | |
| Video Interfaces: | |||
| Camera ISP | additional dual camera schemes | Y | |
| Parallel Interface | Y | Y | |
| Resizer | Y | Y | |
| CCDC | Y | Y | |
| Display Subsystem | Additional dual display schemes | Y | |
| Display Controller (LCD and TV Output) | Y | Y | |
| Remote Frame Buffer Interface (RFBI) | mutually exclusive w/ parallel I/F NDA | NDA | |
| MIPI DSI | NDA | NDA | |
| SDI (Flatlink) | removed | Y | |
| Video Encoder (VENC) | Y | Y | |
| Macrovision | NDA | NDA | |
| Serial Communication: | |||
| McBSP | |||
| McBSP1 | Y | Y | |
| McBSP2 | Y | Y | |
| McBSP3 | Y | Y | |
| McBSP4 | Y | Y | |
| McBSP5 | Y | Y | |
| Multichannel SPI | |||
| McSPI1 | Y | Y | |
| McSPI2 | Y | Y | |
| McSPI3 | Y | Y | |
| McSPI4 | Y | Y | |
| USB OTG | New mentor core 1.8 Rev | Y | |
| USB Host | |||
| USB1 (all features) | Y | Y | |
| USB2 (all features) | Y | Y | |
| USB3 (all features) | Y | Y | |
| HDQ/1-Wire | Y | Y | |
| UART/IrDA/CIR | |||
| UART1 | Y | Y | |
| UART2 | Y | Y | |
| UART3 / IrDA | Y | Y | |
| UART4 | Y; Not available on CUS package due to pinmux restrictions | N | |
| I2C | |||
| I2C1 | Y | Y | |
| I2C2 | Y | Y | |
| I2C3 | Y | Y | |
| I2C4 | Y | Y | |
| Removable Media: | |||
| MMC/SD/SDIO | |||
| MMC1/SDIO1 | only 4 bit interface supported | Y | |
| MMC2/SDIO2 | Y | Y | |
| MMC3/SDIO3 | Y | Y | |
| Memory Stick Pro | NDA-only | NDA-only | |
| Univeral Subscriber Identity Module (USIM) | NDA-only (Not available on CUS package) | NDA-only | |
| Power, Reset, and Clock Management | |||
| All Features | Various PM features updated | Y | |
| Test Interfaces | |||
| JTAG | Y | Y | |
| ETK (trace) | Y | Y | |
| Misc | |||
| GP Timer (x12) | Y | Y | |
| Watchdog Timer (x3) | Y | Y | |
| 32-kHz Sync Timer | Y | Y | |
| GPIO | Y | Y | |
General migration careabouts[edit]
In general, AM37x is a drop in replacement for OMAP35x on same PCB if
1. Camera and displays are used in the same configuration as is the case for OMAP35x
2. If using CBB OMAP35x with non-POP memory:
- SDRC signals are not available at the bottom of CBP [0.4 mm package] in AM/DM37x.
3. MMC1 8-bit mode is not supported on OMAP37x
4. Two discrete components will need to change compared to OMAP35x
- One discrete component (capacitor) needs to be changed but the PCB does not change
- If AVDAC is used then a capacitor is changed to a resistor on the board and other resistor values need to be updated but PCB does not change
In general, 37x will require some SW changes for (see OMAP35x To AM37x Software Migration Guide for more details):
- New pin multiplexing options that have been added based on customer feedback and for ease of use
- Register definitions are changed for some legacy features and new registers are added to enable new features such as new camera and display configurations etc.
- To support new IPs and modules, e.g... ISP2P and ARM r3p2 etc.
- To configure PHYs, DPLLs… i.e. any change related to technology migration.
In general, PCB changes may be needed to enable AM/DM37x enhancements
- To enable new technology features and configurations for 37xx, e.g... Body bias, improved crystal mode jitter, AVDAC etc.
- To enable new peripheral capabilities such as enhanced camera and display support
- To enable use of 720p display on parallel port.
- Some interfaces are removed/updated such as MMC1 being 4 bits vs. 8-bits on OMAP35xx, if used the PCB may require a change
Hardware Migration[edit]
Crystal Oscillator[edit]
AM37x crystal oscillator has a dedicated ground SYS_XTALGND that is used to improve jitter versus OMAP35xx version. Implementation is done in such way that it has no impact on previously designed OMAP35xx PCB. A VSS ball has been updated to the SYS_XTALGND ball. When AM37xx is mounted on a 35xx board, then SYS_XTALGND is connected to the common ground. In that case jitter performance will be the same as OMAP35xx. When AM37xx is mounted on a 37xx optimized board, SYS_XTALGND is connected as shown below and jitter is improved versus OMAP35xx.
TV_OUT (AVDAC) channels[edit]
Device supports composite and S-video through two GS70 channels. Channel1 handles the composite or Luma signals, Channel2 handles the Chroma signals. Channel2 is used only in S-Video mode. TV load detection is only supported on Channel1. Both channels are supplied from the same vdda/vssa balls, only Channel1 reset (CVIDEO1_RSET) is balled out. The GS70 AVDAC does not require a reference voltage decoupling anymore, the OMAP35x tv_vref ball is no longer used for that purpose. The ball is reused to set externally the operating reference current. OMAP35x boards must be reworked to remove the capacitor and replace it with a resistor.
If using TV Out, OMAP35x TV_VREF signal (connected with 0.1uF capacitor to ground) should be replaced with 4.7K resistor to ground for AM37x CVIDEO1_RSET signal.
Decoupling Capacitors[edit]
AM/DM37x requires two balls for the filtering capacitors (logic and array outputs) for EMU/WAKEUP domain where OMAP35x only had one:
- OMAP35x cap_vdd_wkup ball is thus reused for AM/DM37xx cap_vddu_wkup_logic (see below for ball number for your package) with the same capacitor value: 1uF
- OMAP35x cap_vdd_dsi free ball is thus used for AM/DM37xx cap_vddu_array (see below for ball number for your package) with the capacitor value: 1uF
BODY BIAS LDO[edit]
AM/DM37xx integrates a totally new GS70 BODY BIAS LDO designed to operate in 3 modes: Forward Body Bias (FBB to boost performance in weak process), Reverse Body Bias (RBB to reduce leakage in strong process) and Bypass mode (disabled, backward compatibility with OMAP35x). Body bias operates only on the IVA and MPU domains, not the CORE domains. FBB enables ARM frequencies 600MHz-1GHz on AM37x. RBB enables less leakage in strong process silicon, thus reducing power consumption.
The bodybias LDO is supplied by the same ball as the Wakeup LDO and Bandgap REF (vdda_wkup_bg_bb). A stability capacitor on the LDO output is required when the feature is enabled. A new ball was needed in AM/DM37x for cap_vdd_bb_mpu_iva. These balls have been used for that feature:
- U4 on AM37x CBP package
- D6 on AM37x CBC package
- N21 on AM37x CUS package
On OMAP35x CBB and CBC packages, this signal is the analog test output (BG_TESTOUT). OMAP35x boards have this ball NC on the PCB.
On OMAP35x CUS package, this signal is MMC1_DAT5. MMC1 is a maximum 4-bit wide on AM37x, thus this signal would be unused.
If this feature is not needed on AM37x die (Bypass mode), this signal can be left as a NC, and board compatibility would be maintained between OMAP35x and AM37x boards . Customers wanting to enable the FBB or RBB feature (to enable higher ARM frequencies or reduce power consumption) would need a board rework by connecting cap_vdd_bb_mpu_iva to a 1uF capacitor to ground .
GPIO selection[edit]
1. AM/DM37xx integrates a totally new GS70 CAM_PHY which only supports GPI. Hence following pins are GPIO in OMAP35x but are only input pins for AM37x.
| CBP Ball | CBC Ball | CUS Ball | AM37x Pin Mux Mode 4 |
| K28 | P25 | L24 | GPIO_105 [Input Only] |
| L28 | P26 | K24 | GPIO_106 [Input Only] |
| K27 | N25 | J23 | GPIO_107 [Input Only] |
| L27 | N26 | K23 | GPIO_108 [Input Only] |
2. Buffers for GPIO_120-GPIO_127 and GPIO_129 are different between OMAP35x and AM37x. If you have used these GPIOs on the following balls, you may need to include a series resistor (because of different buffer strength) on these signals.
| CPB Ball | CBC Ball | CUS Ball | AM37x DataSheet Name |
| N28 | N19 | M23 | MMC1_CLK/GPIO_120 |
| M27 | L18 | L23 | MMC1_CMD/GPIO_121 |
| N27 | M19 | M22 | MMC1_DAT0/GPIO_122 |
| N26 | M18 | M21 | MMC1_DAT1/GPIO_123 |
| N25 | K18 | M20 | MMC1_DAT2/GPIO_124 |
| P28 | N20 | N23 | MMC1_DAT3/GPIO_125 |
| P27 | M20 | N22 | SIM_IO/GPIO_126 |
| P26 | P17 | NA | SIM_CLK/GPIO_127 |
| R25 | P19 | P24 | SIM_RST/GPIO_129 |
Package specific migration careabouts[edit]
CBB/CBP Package [0.4 mm] Processor[edit]
| PIN_NUMBER | OMAP35x Datasheet Names | AM37x Datasheet |
| AC20 | VSS | GPMC_A11 |
| PIN_NUMBER | NET_NAME | AM37x Datasheet |
| A1 | SYS_OPMCSWS | VSENSE (NC) |
| A2 | POP_NC_A2 | ATESTV (NC) |
| A4 | SDRC_A0 | Reserved (NC) |
| A6 | SDRC_DQS0 | Reserved (NC) |
| A7 | SDRC_D5 | Reserved (NC) |
| A9 | SDRC_D7 | Reserved (NC) |
| A10 | SDRC_DQS2 | Reserved (NC) |
| A11 | SDRC_D21 | Reserved (NC) |
| A19 | SDRC_D25 | Reserved (NC) |
| A20 | SDRC_DQS3 | Reserved (NC) |
| A21 | SDRC_D29 | Reserved (NC) |
| AA14 | VDDS_WKUP_BG | VDDA_WKUP_BG_BB |
| AA15 | CAP_VDD_WKUP | CAP_VDDU_WKUP_LOGIC |
| AA26 | VSS_SDI | Reserved (NC) |
| AE27 | VDDS_SDI | Reserved (NC) |
| AH20 | CAP_VDD_DSI | CAP_VDDU_ARRAY |
| B1 | SYS_IPMCSWS | IFORCE (NC) |
| B3 | SDRC_A2 | Reserved (NC) |
| B4 | SDRC_A1 | Reserved (NC) |
| B6 | SDRC_D2 | Reserved (NC) |
| B7 | SDRC_DM0 | Reserved (NC) |
| B9 | SDRC_D6 | Reserved (NC) |
| B10 | SDRC_D17 | Reserved (NC) |
| B11 | SDRC_DM2 | Reserved (NC) |
| B13 | SDRC_D22 | Reserved (NC) |
| B19 | SDRC_D26 | Reserved (NC) |
| B20 | SDRC_D27 | Reserved (NC) |
| B21 | SDRC_D30 | Reserved (NC) |
| C1 | SDRC_A8 | Reserved (NC) |
| C2 | SDRC_A7 | Reserved (NC) |
| C3 | SDRC_A6 | Reserved (NC) |
| C4 | SDRC_A4 | Reserved (NC) |
| C5 | SDRC_A3 | Reserved (NC) |
| C6 | SDRC_D1 | Reserved (NC) |
| C8 | SDRC_D3 | Reserved (NC) |
| C9 | SDRC_D4 | Reserved (NC) |
| C11 | SDRC_D18 | Reserved (NC) |
| C12 | SDRC_D20 | Reserved (NC) |
| C18 | SDRC_D24 | Reserved (NC) |
| C20 | SDRC_DM3 | Reserved (NC) |
| C21 | SDRC_D31 | Reserved (NC) |
| D1 | SDRC_A12 | Reserved (NC) |
| D2 | SDRC_A11 | Reserved (NC) |
| D3 | SDRC_A10 | Reserved (NC) |
| D4 | SDRC_A9 | Reserved (NC) |
| D5 | SDRC_A5 | Reserved (NC) |
| D6 | SDRC_D0 | Reserved (NC) |
| D11 | SDRC_D16 | Reserved (NC) |
| D12 | SDRC_D19 | Reserved (NC) |
| D14 | SDRC_D23 | Reserved (NC) |
| D20 | SDRC_D28 | Reserved (NC) |
| E1 | SDRC_A14 | Reserved (NC) |
| E2 | SDRC_A13 | Reserved (NC) |
| P26 | MMC1_DAT5 | SIM_CLK |
| P27 | MMC1_DAT4 | SIM_IO |
| R25 | MMC1_DAT7 | SIM_RST |
| R27 | MMC1_DAT6 | SIM_PWRCTRL |
| U4 | BG_TESTOUT | CAP_VDD_BB_MPU_IVA |
| W26 | TV_VREF | CVIDEO1_RSET |
| W27 | TV_VFB2 | CVIDEO2_VFB |
| W28 | TV_OUT2 | CVIDEO2_OUT |
| Y17 | VSS | SYS_XTALGND |
| Y27 | TV_VFB1 | CVIDEO1_VFB |
| Y28 | TV_OUT1 | CVIDEO1_OUT |
CBC Package [0.5 mm] Processor[edit]
| PIN_NUMBER | 35xx Datasheet Names | 37xx Datasheet Names |
| A2 | SYS_OPMCSWS (leave as NC) | VSENSE (leave as NC) |
| A4 | NC | GPMC_A11 |
| AD18 | VDDS_CSI2 | VDDS_CSIPHY2 |
| AE19 | CAP_VDD_DSI | CAP_VDDU_ARRAY |
| AF1 | NC | ATESTV (leave as NC) |
| AF23 | VSS | SYS_XTALGND |
| B1 | SYS_IPMCSWS (leave as NC) | IFORCE (leave as NC) |
| D6 | BG_TESTOUT | CAP_VDD_BB_MPU_IVA |
| K13 | VDDS_DPLL | VDDA_DPLLS_DLL |
| K14 | CAP_VDD_WKUP | CAP_VDDU_WKUP_LOGIC |
| L19 | VSS_CSIB | VSSA_CSIPHY1 |
| L20 | VDDS_CSIB | VDDA_CSIPHY1 |
| M20 | MMC1_DAT4 | SIM_IO |
| P17 | MMC1_DAT5 | SIM_CLK |
| P18 | MMC1_DAT6 | SIM_PWRCTRL |
| P19 | MMC1_DAT7 | SIM_RST |
| U24 | TV_VFB2 | CVIDEO2_VFB |
| V23 | TV_VREF | CVIDEO1_RSET |
| V26 | TV_OUT2 | CVIDEO2_OUT |
| W14 | VDDS_WKUP_BG | VDDS_WKUP_BG_BB |
| W25 | TV_VFB1 | CVIDEO1_VFB |
| W26 | TV_OUT1 | CVIDEO1_OUT |
CUS Package [0.65 mm] Processor[edit]
| PIN_NUMBER | 35x Datasheet Name | 37x DataSheet Name |
| AA23 | TV_OUT2 | CVIDEO2_OUT |
| AB23 | TV_VFB1 | CVIDEO1_VFB |
| AB24 | TV_OUT1 | CVIDEO1_OUT |
| N20 | MMC1_DAT6/GPIO_128 | CAP_VDDU_ARRAY |
| N21 | MMC1_DAT5/GPIO_127 | CAP_VDD_BB_MPU_IVA |
| N22 | MMC1_DAT4/GPIO_126 | GPIO_126 |
| P24 | MMC1_DAT7/GPIO_129 | GPIO_129 |
| W15 | VSS | SYS_XTALGND |
| Y12 | CAP_VDD_WKUP | cap_vddu_wkup_logic |
| Y23 | TV_VFB2 | CVIDEO2_VFB |
| Y24 | TV_VREF | CVIDEO1_RSET |
Operating conditions careabouts[edit]
VDD1 Recommended Operating condition Comparison[edit]
| OPP | ARM Frequency (MHz) |
DSP Frequency (MHz) |
Voltage (V) |
| OPP6 | 720 | 520 | 1.35 |
| OPP5 | 600 | 430 | 1.35 |
| OPP4 | 550 | 400 | 1.27 |
| OPP3 | 500 | 360 | 1.2 |
| OPP2 | 250 | 180 | 1.06 |
| OPP1 | 125 | 90 | 0.985 |
Note: Please refer to the OMAP35x Datasheet for the latest OPP values.
| OPP | ARM Frequency (MHz) |
DSP Frequency (MHz) |
Voltage (V) |
| OPP1G | 1000 | 800 | 1.35 |
| OPP130 | 800 | 660 | 1.2 |
| OPP100 | 600 | 520 | 1.1 |
| OPP50 | 300 | 260 | 0.9735 |
Note: Please refer to the AM/DM37x Datasheet for the latest OPP values.
VDD2 Recommended Operating condition Comparison[edit]
| OPP | L3_ICLK Frequency (MHz) |
Voltage (V) |
| OPP3 | 166 | 1.15 |
| OPP2 | 133 | 1.06 |
| OPP1 | 100 | 0.985 |
Note: Please refer to the AM/DM37x Datasheet for the latest OPP values.
| OPP | L3_ICLK Frequency (MHz) |
Voltage (V) |
| OPP100 | 200 | 1.15 |
| OPP50 | 100 | 0.9735 |
Note: Please refer to the AM/DM37x Datasheet for the latest OPP values.
Max current rating comparison[edit]
| PARAMETER | OMAP35xx | AM/DM37xx | |||
| MAX | UNIT | MAX | UNIT | ||
| SIGNAL | DESCRIPTION | ||||
| vdd_mpu_iva(1) | Maximum current rating for MPU / IVA2 domain | 1200 | mA | 1400 | mA |
| vdd_core(1) | Maximum current rating for OMAP core domain | 490 | mA | 300 | mA |
| vdds_io | Maximum current rating for 1.8-V I/O macros | 63 | mA | 60 | mA |
| vdds_mem | Maximum current rating for memory buffers | 37 | mA | 35 | mA |
| vdds_sdmmc1 | Maximum current rating for SDMMC1 dual voltage buffers | 20 | mA | 20 | mA |
| vdds_sim | Maximum current rating for SIM dual voltage buffers | 2 | mA | 2 | mA |
| vdda_wkup_bg_bb | Maximum current rating for wake-up, bandgap and VBB LDOs | 6 | mA | 5 | mA |
| vdda_dac | Maximum current rating for video buffers and DAC | 65 | mA | 60 | mA |
| vdda_dplls_dll | Maximum current rating for MPU, IVA, core DPLLs and DLL | 30 | mA | 30 | mA |
| vdda_dpll_per | Maximum current rating for DPLLs (peripherals) | 10 | mA | 10 | mA |
| vdda_sram | Maximum current rating for SRAM LDOs (common) | 41 | mA | 41 | mA |
(1) These values are for maximum performance devices (OMAP3530/DM3730). Other devices and performance points will have smaller values.
Voltage decoupling comparison[edit]
| PARAMETER | MAXFREQUENCY | OMAP35xx | AM/DM37xx | ||||||
| MIN | TYP | MAX | UNIT | MIN | TYP | MAX | UNIT | ||
| Cvdds_io | - | 50 | 100 | 150 | nF | 200 | 400 | 600 | nF |
| Cvdd_mpu_iva (1) | - | 50 | 100 | 150 | nF | 0.6 | 1.2 | 1.8 | µF |
| Cvdd_core | - | 50 | 100 | 150 | nF | 0.6 | 1.2 | 1.8 | µF |
| Cvdds_mem | - | 50 | 100 | 150 | nF | 350 | 700 | 1050 | nF |
| Cvdds_sdmmc1 | 140 | 50 | 100 | 150 | nF | 50 | 100 | 150 | nF |
| Cvdds_sim | 140 | 50 | 100 | 150 | nF | 50 | 100 | 150 | nF |
| Cvdda_sram | 40 | 50 | 100 | 150 | nF | 110 | 220 | 330 | nF |
| Cvdda_dplls_dll | 140 | 50 | 100 | 150 | nF | 50 | 100 | 150 | nF |
| Cvdda_dpll_per | 140 | 50 | 100 | 150 | nF | 50 | 100 | 150 | nF |
| Cvdda_dac | 100 | 50 | 100 | 150 | nF | 50 | 100 | 150 | nF |
| Cvdda_csiphy1 | 140 | 110 | 220 | 330 | nF | 110 | 220 | 330 | nF |
| Cvdda_csiphy2 | 140 | 110 | 220 | 330 | nF | 110 | 220 | 330 | nF |
| Cvdda_dsi | 140 | 110 | 220 | 330 | nF | 110 | 220 | 330 | nF |
| Cvdds_sdi | - | 110 | 220 | 330 | nF | NA | NA | NA | nF |
| Cvdda_wkup_bg_bb | TBD | 50 | 100 | 150 | nF | 240 | 470 | 700 | nF |
| Ccap_vdd_sram_mpu_iva | - | 0.7 | 1.0 | 1.3 | μF | 0.7 | 1.0 | 1.3 | μF |
| Ccap_vdd_sram_core | - | 0.7 | 1.0 | 1.3 | μF | 0.7 | 1.0 | 1.3 | μF |
| Ccap_vddu_wkup_logic | - | 0.7 | 1.0 | 1.3 | μF | 0.7 | 1.0 | 1.3 | μF |
| Ccap_vddu_array | - | NA | NA | NA | μF | 0.7 | 1.0 | 1.3 | μF |
| Ccap_vdd_bb_mpu_iva | - | NA | NA | NA | μF | 0.7 | 1.0 | 1.3 | μF |
(1) For more information regarding the vdd_mpu_iva decoupling capacitance recommendations for maximum performance DM3730 devices, see the OMAP3630_VDD_MPU_IVA_PDN_APN application note.
Feature Enhancements[edit]
Increase SDRC / L3/ GPMC clock frequency[edit]
Supports LPDDR1 memories up to 200MHz due to SDRC and L3 frequency increase from 166MHz to 200MHz. 37xx still supports legacy frequency plan of OMAP35xx. GPMC Frequency also would be increased from 100 to 83 MHz.
Increase with SGX clock frequency[edit]
SGX530 is now able to run up to 192MHz. PRCM.CM_CLKSEL_SGX register has been updated to support additional clocking scheme. New definition of this register is backward compatible with 35xx definition, i.e. values defined for 35xx have the same meaning in 37xx. Register impacted is "CM_CLKSEL_CORE". This clock is provided by PRM_192M_ALOWON_CLK clock.
Support linked list on system DMA[edit]
Some existing registers have been updated and are backward compliant with 35xx. For instance DMA_CAPS_4 has been updated to reflect new DMA capabilities. If masking of reserved bits is not applied in 35xx SW then value will be different when ported to 37xx. Additional registers have been added to support linked list feature.
Support pre-multiplied alpha blending[edit]
Display supports pre-multiplied alpha RGB data coming from some HLOSes. When those data are sent to display controller, hardware alpha multiplication in display controller can be disabled.
Support 720p input in ISP2P[edit]
ISP accepts a pixel clock up to 150MHz with 8bits parallel interface instead of 130MHz on OMAP35xx
DPLL[edit]
New bit widths are available for setting divider Bits following registers are impacted.
CORE_CM (CM_CLKSEL_CORE),
SGX_CM (CM_C LKSEL_SGX),
ClockC_Control_Reg_CM (CM_CLKEN_PLL, CM_CLKEN2_PLL, CM_CLKSEL2_P LL, CM_CLKSEL3_P LL),
DSS_CM (CM_CLKSEL_DSS),
CAM_CM (CM_C LKSEL_CAM),
EMU_CM (CM_CLKSEL1_EMU),
PER_CM (CM_FCLKEN_PER,CM_ICLKEN_PER, CM_IDLEST_PE R, CM_AUTOIDLE_ PER).
DPLL4 changed to low jitter type DPLL[edit]
Bits have been added to DPLL programming model. Those bits are controlled by the PRCM. DPLL4 is changed to new type for low-jitter. New source clock control configs are included.DPLL4 ramping time control removed. Multipler value increased to 12 bit wide vs 11 bit in OMAP35x.
IVA2_CM (CM_CLKEN _PLL _IVA 2), MPU_CM (CM_CLKEN _PLL _MPU), CORE_CM (CM_CLKSEL_CORE), SGX_CM (CM_C LKSEL_SGX), ClockC_Control_Reg_CM (CM_CLKEN_PLL, CM_CLKEN2_PLL, CM_CLKSEL2_P LL, CM_CLKSEL3_P LL), DSS_CM (CM_CLKSE L_DSS), CAM_CM (CM_C LKSE L_CAM), EMU_CM (CM_CLKSE L1_EMU), PER_CM (CM_FCLKEN_PER, CM_ICLKEN_PER, CM_IDLES T_PE R, CM_A UTOI DLE_ PER).
DLL[edit]
DLL in AM37x does not support 72deg phase shift mode. Only 90deg phase shift is available.
Additional UART instance[edit]
UART4 added which is backward compatible with UART1/UART2 configuration. This is available only in CBP & CBC packages, since muxed behind GPMC_wait pins which are not availble in CUS package. Refer below for more details.
Pinmultiplexing updates[edit]
Additional DSS multiplexing schemes[edit]
Backward compatibility is maintained if your pixel clock on DSS interface is <= 60 MHz. But if your pixel clock is higher, 60< PCLK <= 75 MHz, you would need to use the High Speed Mode pinmux scheme. For all new AM37x designs, High Speed Mode pinmux scheme should be used.
| OMAP35x | AM/DM 37x | ||
| Parallel mode 24-bit | Parallel mode 24-bit | ||
| Signal Name | PCLK <= 75 MHz [Legacy Mode] | PCLK <= 60 MHz [Legacy Mode] | PCLK <= 75 MHz [High Speed Mode] |
| dss_hsync/rfbi_cs0 | DSS | DSS | DSS |
| dss_vsync/rfbi_wr | |||
| dss_pclk/rfbi_rd | |||
| dss_acbias/rfbi_a0 | |||
| dss_data0/rfbi_da0 | DSS [0-5] |
DSS [0-5] |
NC |
| dss_data1/rfbi_da1 | |||
| dss_data2/rfbi_da2 | |||
| dss_data3/rfbi_da3 | |||
| dss_data4/rfbi_da4 | |||
| dss_data5/rfbi_da5 | |||
| VDDS | pwr rail VIO | pwr rail VIO | pwr rail VIO |
| VSS | GND | GND | GND |
| dss_data6/rfbi_da6 | DSS [6-17] |
DSS [6-17] |
DSS [6-17] |
| dss_data7/rfbi_da7 | |||
| dss_data8/rfbi_da8 | |||
| dss_data9//rfbi_da9 | |||
| dss_data10/rfbi_da10 | |||
| dss_data11/rfbi_da11 | |||
| dss_data12/rfbi_da12 | |||
| dss_data13/rfbi_da13 | |||
| dss_data14/rfbi_da14 | |||
| dss_data15/rfbi_da15 | |||
| dss_data16/rfbi_te_vsync0 | |||
| dss_data17/rfbi_hsync0 | |||
| dss_data18/rfbi_te_vsync1 | DSS [18-23] |
DSS [18-23] |
DSS [0-5] |
| dss_data19/rfbi_hsync1 | |||
| dss_data20/rfbi_cs1 | |||
| dss_data21 | |||
| dss_data22 | |||
| dss_data23 | |||
| sys_boot0 | NC |
NC |
DSS [18-23] |
| sys_boot1 | |||
| sys_boot3 | |||
| sys_boot4 | |||
| sys_boot5 | |||
| sys_boot6 | |||
UART4 multiplexing scheme[edit]
UART4 (TX/RX) has been multiplexed behind GPMC wait pins. Since these pins are not availble on CUS package UART4 instance is not available in CUS package. It is available on CBP & CBC package at following pins.
| Mux0 | Mux1 | Mux2 |
| gpmc_wait2 | uart4_tx | |
| gpmc_wait3 | sys_ndmareq1 | uart4_rx |
UART3 pinmux Additional UART3 multiplexing scheme[edit]
UART3 (TX/RX) has been multiplexed (muxmode 2) on pads DSS_DATA8/9.
| CBP | CBP Ball Bottom | CBP Ball Top | CBC | CBC Ball Bottom | CBC Ball Top | CUS | CUS Ball Bottom | Mux0 | Mux2 |
| DSS_DATA8 | F27 | NA | DSS_DATA8 | H26 | NA | DSS_DATA8 | E24 | dss_data8 | uart3_rx_irrx |
| DSS_DATA9 | G26 | NA | DSS_DATA9 | J26 | NA | DSS_DATA9 | F23 | dss_data9 | uart3_tx_irtx |
Additional DRM_MSECURE multiplexing scheme[edit]
DRM_MSECURE has been multiplexed (muxmode 1) on pads ETK D8 and D12.
| CBP | CBP Ball Bottom | CBP Ball Top | CBC | CBC Ball Bottom | CBC Ball Top | CUS | CUS Ball Bottom | Interface Mode 0 | Datasheet Mux Mode0 | Mux0 | *Mux0: Power domain |
*Mux0: Dir |
Interface Mode 1 | Mux1 |
| ETK_D8 | AF9 | NA | ETK_D8 | AA4 | NA | ETK_D8 | AC4 | ETK | etk_d8 | EMU | O | SYS | sys_drm_msecure | |
| ETK_D9 | AG9 | NA | ETK_D9 | V2 | NA | ETK_D9 | AD5 | ETK | etk_d9 | EMU | O | SYS | sys_secure_indicator | |
| ETK_D12 | AG7 | NA | ETK_D12 | AE6 | NA | ETK_D12 | AC10 | ETK | etk_d12 | EMU | O | SYS | sys_drm_msecure |
Additional UART2 multiplexing scheme[edit]
UART2 (full 4-wire interface) has been multiplexed (muxmode 5) on ULPI. This allows the customer to trace out on UART2 (in a carkit manner) while using UART3 for other functional reasons.
| CBP | CBP Ball Bottom | CBP Ball Top | CBC | CBC Ball Bottom | CBC Ball Top | CUS | CUS Ball Bottom | Interface Mode 0 | Datasheet Mux Mode0 | Mux0 | Mux2 | Mux5 |
| HSUSB0_DATA0 | T27 | NA | HSUSB0_DATA0 | V20 | NA | HSUSB0_DATA0 | T24 | HSUSB0 | hsusb0_data0 | uart3_tx_irtx | uart2_tx | |
| HSUSB0_DATA1 | U28 | NA | HSUSB0_DATA1 | Y20 | NA | HSUSB0_DATA1 | T23 | HSUSB0 | hsusb0_data1 | uart3_rx_irrx | uart2_rx | |
| HSUSB0_DATA2 | U27 | NA | HSUSB0_DATA2 | V18 | NA | HSUSB0_DATA2 | U24 | HSUSB0 | hsusb0_data2 | uart3_rts_sd | uart2_rts | |
| HSUSB0_DATA3 | U26 | NA | HSUSB0_DATA3 | W20 | NA | HSUSB0_DATA3 | U23 | HSUSB0 | hsusb0_data3 | uart3_cts_rctx | uart2_cts |
ROM Code updates[edit]
ASIC ID Descriptor update[edit]
ASIC-ID descriptor has been updated to discriminate AM/DM37xx from OMAP35xx. AM/DM37xx ASIC-ID is 0x37xx. If this value is used by the SW, then it has to be updated to take into account this new value.
ASIC ID Timeout update[edit]
ASIC-ID time-out has been increased from 300ms to 3s.
USB Descriptor update[edit]
USB descriptor has been to discriminate 37xx from 35xx during USB boot. Id Product field has been updated to 0xD00E. String descriptor has been updated to "AM/DM37xx". Those new values have to be taken into account by SW managing USB boot on HOST side.
Improved OneNAND Memory support[edit]
OMAP35xx ROM code was able to perform 1-bit error correction to be able to boot from SLC NANDs which only required 1-bit ECC. AM/DM37xx ROM code is now compatible with oneNANDs that support 4-bit error correction. Note that with this enhancement, the ROM code does not do the 4-bit error correction. It relies on the oneNAND on-chip ECC. This AM/DM37xx ROM enhancement only affects oneNAND devices. For all other NAND devices, only 1-bit ECC is supported in the ROM.
New Boot Modes supported[edit]
A new boot configuration (configuration #28) has been added on 37xx. This configuration was marked as reserved on OMAP35xx. This configuration is as follow
- sys.boot[5] = 0
- 1st: MMC2 (with VRMMC1 enabled on PMU)
- 2nd: USB
- 3rd: UART3
- 4th: None
- sys.boot[5] = 1
- 1st: USB
- 2nd: UART3
- 3rd: MMC2 (with VRMMC1 enabled on PMU)
- 4th: None
L2 cache disabled after PoR / Warm Reset[edit]
Revision update[edit]
CortexA8[edit]
ARM Cortex-A8 r3p2 implements bug fixes that have been found in Cortex-A8 r2p3 and intermediate releases to r3p2. New revision used in AM/DM37xx comes with additional L1 cache memories. Data and instruction caches have been extended from 16KB each to 32KB each. This update has an impact on cache management software.
Errata Fixes:
- 430973: Stale prediction on replaced interworking branch causes Cortex-A8 to execute in the wrong ARM/Thumb state
- 451027: Neon loads or stores may incorrectly report a precise data abort under certain conditions
- 621766: Under a specific set of conditions, executing a sequence of NEON or vfp load instructions can cause processor deadlock
SGX530[edit]
37xx implements 1.2.5 v of SGX530TM core. This includes bug fixes associated with cache management.
Removed Features[edit]
8 data bits on MMC1[edit]
MMC1 interface supports MMC cards with up to 4 data bits.
SDI (Flatlink)[edit]
The seriel digital interface ("Flatlink") has been silently removed. Use MIPI/DSI or connect a flatlink transmitter to the parallel interface.
Errata Fixes[edit]
UART[edit]
Errata 1.167: UART not asserting its TX DMA request when RX FIFO is not empty
GPIO[edit]
Errata 1.157: Pull-up not maintained on pin corresponding to GPIO_28/29 during padconf restore
Errata 1.158: GPIO pad spurious transition (glitch/spike) upon wake up from system OFF mode
CAMERA[edit]
Errata 1.136: ISP: LSC issue when used concurrently with resizer
Errata 1.139: ISP CCDC DRAM Read-Port Issue
Errata 1.140: ISP Lens Shading Correction Issue
USB Host Controller[edit]
Errata 1.152: USB TLL Save-and-Restore Issue
Errata 1.154: Illegal RXCMD sent by HSUSB TLL Module
Errata 1.155: EHCI controller- Issue in suspend resume protocol
Errata 1.161: USB Host/TLL issue when waking up from device OFF mode
USB OTG Controller[edit]
Errata 1.130: USB DMA cannot handle concurrent channels
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