OMAP35x-AM37x-DM37x with TPS65023: Design In Guide

Abstract

This document details the design considerations of a Power Management Unit solution for the OMAP35x or AM/DM37x processors using the TPS65023 device.

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Introduction

The OMAP35x and AM/DM37x Applications Processors have a diverse set of power management features which potentially enable lower cost power solutions based on your application. This design-in guide describes a power solution based on the TPS65023 device. This guide can be used to evaluate this solution for your design, or help you make decisions when designing in this solution.

Power Requirements and Features of OMAP35x and AM/DM37x

A TPS65023 based power solution can power any device in the OMAP35x family (OMAP3503, OMAP3515, OMAP3525, OMAP3530) or the AM/DM37x family (AM3703, AM3715, DM3725, DM3730). The following section describes the specifications and power management features of these devices.

Power Specifications

The following tables detail the power requirements for each OMAP35x and AM/DM37x device that is supported by a TPS65023 based power solution.

OMAP3503

	Power Rail	Voltage	Tolerance	Imax (mA)	Sequencing order
Core	VDD_MPU	0.95V, 1.0V, 1.2V, 1.27V, 1.35V(*)	+/- 5%	680	4
Core	VDD_CORE	0.95V, 1.0V, 1.15V (*)	+/- 5%	320	3
I/O	VDDS, VDDS_WKUP_BG, VDDS_MEM, VDDS_SRAM	1.8V	+/- 5%	147	1
I/O	VDDS_DPLL_PER, VDDS_DPLL_DLL	1.8V	+/- 5%	40	2
I/O	VDDA_DAC	1.8V	+/- 5%	65	After reset
I/O	VDDS_MMC1, VDDS_MMC1A	1.8V	+/- 5%	22	After reset (see Power Up sequencing for more info)
		3.0V	+/- 10%

Power numbers above assume SmartReflex AVS is implemented.

^(*) Refer to the latest OMAP35x datasheet for the most current voltage values

OMAP3515

	Power Rail	Voltage	Tolerance	Imax (mA)	Sequencing order
Core	VDD_MPU	0.95V, 1.0V, 1.2V, 1.27V, 1.35V (*)	+/- 5%	680	4
Core	VDD_CORE	0.95V, 1.0V, 1.15V (*)	+/- 5%	430	3
I/O	VDDS, VDDS_WKUP_BG, VDDS_MEM, VDDS_SRAM	1.8V	+/- 5%	147	1
I/O	VDDS_DPLL_PER, VDDS_DPLL_DLL	1.8V	+/- 5%	40	2
I/O	VDDA_DAC	1.8V	+/- 5%	65	After reset
I/O	VDDS_MMC1, VDDS_MMC1A	1.8V	+/- 5%	22	After reset (see Power Up Sequencing for more info)
		3.0V	+/- 10%

Power numbers above assume SmartReflex AVS is implemented.

^(*) Refer to the latest OMAP35x datasheet for the most current voltage values

OMAP3525

	Power Rail	Voltage	Tolerance	Imax (mA)	Sequencing order
Core	VDD_MPU_IVA	0.95V, 1.0V, 1.2V, 1.27V, 1.35V (*)	+/- 5%	1140	4
Core	VDD_CORE	0.95V, 1.0V, 1.15V (*)	+/- 5%	330	3
I/O	VDDS, VDDS_WKUP_BG, VDDS_MEM, VDDS_SRAM	1.8V	+/- 5%	147	1
I/O	VDDS_DPLL_PER, VDDS_DPLL_DLL	1.8V	+/- 5%	40	2
I/O	VDDA_DAC	1.8V	+/- 5%	65	After reset
I/O	VDDS_MMC1, VDDS_MMC1A	1.8V	+/- 5%	22	After reset (see Power Up Sequencing for more info)
		3.0V	+/- 10%

Power numbers above assume SmartReflex AVS is implemented.

^(*) Refer to the latest OMAP35x datasheet for the most current voltage values

OMAP3530

	Power Rail	Voltage	Tolerance	Imax (mA)	Sequencing order
Core	VDD_MPU_IVA	0.95V, 1.0V, 1.2V, 1.27V, 1.35V (*)	+/- 5%	1140	4
Core	VDD_CORE	0.95V, 1.0V, 1.15V (*)	+/- 5%	430	3
I/O	VDDS, VDDS_WKUP_BG, VDDS_MEM, VDDS_SRAM	1.8V	+/- 5%	147	1
I/O	VDDS_DPLL_PER, VDDS_DPLL_DLL	1.8V	+/- 5%	40	2
I/O	VDDA_DAC	1.8V	+/- 5%	65	After reset
I/O	VDDS_MMC1, VDDS_MMC1A	1.8V	+/- 5%	22	After reset (see Power Up Sequencing for more info)
		3.0V	+/- 10%

Power numbers above assume SmartReflex AVS is implemented.

^(*) Refer to the latest OMAP35x datasheet for the most current voltage values

AM3703

	Power Rail	Voltage	Tolerance	Imax (mA)	Sequencing order
Core	VDD_MPU	0.95V, 1.0V, 1.2V, 1.27V, 1.35V(*)	+/- 5%	740	4
Core	VDD_CORE	0.95V, 1.0V, 1.15V (*)	+/- 5%	230	3
I/O	VDDS, VDDS_WKUP_BG, VDDS_MEM, VDDS_SRAM	1.8V	+/- 5%	141	1
I/O	VDDS_DPLL_PER, VDDS_DPLL_DLL	1.8V	+/- 5%	40	2
I/O	VDDA_DAC	1.8V	+/- 5%	60	After reset
I/O	VDDS_MMC1, VDDS_MMC1A	1.8V	+/- 5%	22	After reset (see Power Up Sequencing for more info)
		3.0V	+/- 10%

Power numbers above assume SmartReflex AVS is implemented.

^(*) Refer to the latest AM37x datasheet for the most current voltage values

AM3715

	Power Rail	Voltage	Tolerance	Imax (mA)	Sequencing order
Core	VDD_MPU	0.95V, 1.0V, 1.2V, 1.27V, 1.35V (*)	+/- 5%	740	4
Core	VDD_CORE	0.95V, 1.0V, 1.15V (*)	+/- 5%	300	3
I/O	VDDS, VDDS_WKUP_BG, VDDS_MEM, VDDS_SRAM	1.8V	+/- 5%	141	1
I/O	VDDS_DPLL_PER, VDDS_DPLL_DLL	1.8V	+/- 5%	40	2
I/O	VDDA_DAC	1.8V	+/- 5%	60	After reset
I/O	VDDS_MMC1, VDDS_MMC1A	1.8V	+/- 5%	22	After reset (see Power Up Sequencing for more info)
		3.0V	+/- 10%

Power numbers above assume SmartReflex AVS is implemented.

^(*) Refer to the latest AM37x datasheet for the most current voltage values

DM3725

	Power Rail	Voltage	Tolerance	Imax (mA)	Sequencing order
Core	VDD_MPU_IVA	0.95V, 1.0V, 1.2V, 1.27V, 1.35V (*)	+/- 5%	1400	4
Core	VDD_CORE	0.95V, 1.0V, 1.15V (*)	+/- 5%	230	3
I/O	VDDS, VDDS_WKUP_BG, VDDS_MEM, VDDS_SRAM	1.8V	+/- 5%	141	1
I/O	VDDS_DPLL_PER, VDDS_DPLL_DLL	1.8V	+/- 5%	40	2
I/O	VDDA_DAC	1.8V	+/- 5%	60	After reset
I/O	VDDS_MMC1, VDDS_MMC1A	1.8V	+/- 5%	22	After reset (see Power Up Sequencing for more info)
		3.0V	+/- 10%

Power numbers above assume SmartReflex AVS is implemented.

^(*) Refer to the latest DM37x datasheet for the most current voltage values

DM3730

	Power Rail	Voltage	Tolerance	Imax (mA)	Sequencing order
Core	VDD_MPU_IVA	0.95V, 1.0V, 1.2V, 1.27V, 1.35V (*)	+/- 5%	1400	4
Core	VDD_CORE	0.95V, 1.0V, 1.15V (*)	+/- 5%	300	3
I/O	VDDS, VDDS_WKUP_BG, VDDS_MEM, VDDS_SRAM	1.8V	+/- 5%	141	1
I/O	VDDS_DPLL_PER, VDDS_DPLL_DLL	1.8V	+/- 5%	40	2
I/O	VDDA_DAC	1.8V	+/- 5%	60	After reset
I/O	VDDS_MMC1, VDDS_MMC1A	1.8V	+/- 5%	22	After reset (see Power Up Sequencing for more info)
		3.0V	+/- 10%

Power numbers above assume SmartReflex AVS is implemented.

^(*) Refer to the latest DM37x datasheet for the most current voltage values

Power-Up Sequencing

The figure below shows the power-up sequencing requirements of OMAP35x or AM/DM37x. Here is a description of the power-up sequence:

1. VDDS_WKUP_BG, VDDS_MEM, VDDS, and VDDS_SRAM are all 1.8V rails and are tied to the same power supply. These are ramped first, ensuring a valid level on the IO domain. In our example block diagram, these rails are powered by the DCDC3 in the TPS65023.

2. During the entire power up sequence, the power on reset signal SYS_NRESPWRON must be held low until all rails and clocks are stable. This is accomplished using the RESPWRON output of the TPS65023 and the appropriate capacitor connected to T_RESPWRON to achieve the desired delay time. See SYS_nRESPWRON timing section for more information.

3. Both the 32KHz and the high frequency clock need to start oscillating and be stable.

4. After 1.8V is stabilized, VDD_CORE can start ramping.

5. After VDD_CORE is stabilized, VDD_MPU_IVA can start ramping.

6. After 1.8V is stabilized, VDDS_DPLL_DLL and VDDS_DPLL_PER (rails are tied to the same power supply) can ramp during or after VDD_CORE and VDD_MPU_IVA ramp.

7. Once all of the above power rails have stabilized, and 32KHz and the high frequency clock have stabilized, then SYS_NRESPWRON can be released.

8. Other power supplies, such as VDDS_MMC1, VDDS_MMC1A, VDDS_DAC, etc. can be turned on or off depending on the application.

Power Down Sequencing

When using the TPS65023 power solution, power down is achieved by removing the input voltage VBAT. When this occurs, all voltages will ramp down at the same time, and the ramp rate of each voltage will generally be determined by the load on that voltage.

During power down, all signals driving OMAP35x or AM/DM37x should have a voltage level equal or less than the I/O voltage of OMAP35x or AM/DM37x to avoid driving pins that are unpowered. For example, the below schematic example shows the 32KHz clock gated by a 1.8V Power Good signal. This ensures that this clock circuit does not drive the OMAP35x or AM/DM37x input clock pins when the 1.8V is removed from OMAP35x or AM/DM37x.

OMAP35x/AM37x power management features

The OMAP35x and AM/DM37x Application Processors have a rich set of features that make aggressive power optimizations feasible in a user application. These features include DVFS (Dynamic Voltage Frequency Scaling) and SmartReflex AVS (Adaptive Voltage Scaling). Both of these features allow for the lowest power operation depending on the OMAP35x and AM/DM37x processing requirements. In short, DVFS allows the user to change between the OMAP35x and AM/DM37x operating points (voltages) depending on the device operating frequency. Depending on your application, you may want to be able to move among these voltage levels during operation to reduce power consumption. SmartReflex AVS optimizes each of these operating points based on wafer process differences, temperature, and silicon degradation.

Dynamic Voltage and Frequency Scaling (DVFS)

DVFS is a power management technique used while active processing is going on in the system-on-chip (SoC). This technique matches the operating frequency of the hardware to the performance requirement of the active application scenario. Whenever clock frequencies are lowered, operating voltages can be lowered as well to achieve power savings. OMAP35x and AM/DM37x supports this technique on VDD_MPU_IVA and VDD_CORE power rails by defining discrete voltage values for these power rails and the accompanying maximum clock frequencies allowed for the modules supplied by those power rails. Each operating voltage and accompanying maximum clock frequency specification is called an Operating Performance Point (OPP). The tables below show the OPP definitions for VDD_MPU_IVA and VDD_CORE.

VDD1 OPP definition table

OMAP35x VDD1 Operating Performance Points

OPP	ARM Frequency (MHz)	DSP Frequency (MHz)	Voltage (V)
OPP6	720	520	1.35
OPP5	600	430	1.35
OPP4	550	400	1.27
OPP3	500	360	1.2
OPP2	250	180	1.06
OPP1	125	90	0.985

Note: Please refer to the OMAP35x Datasheet for the latest OPP values.

AM37x VDD1 Operating Performance Points

OPP	ARM Frequency (MHz)	DSP Frequency (MHz)	Voltage (V)
OPP1G	1000	800	1.35
OPP130	800	660	1.2
OPP100	600	520	1.1
OPP60	300	260	0.9735

Note: Please refer to the AM/DM37x Datasheet for the latest OPP values.

VDD2 OPP definition table

OMAP35x VDD2 Operating Performance Points

OPP	L3_ICLK Frequency (MHz)	Voltage (V)
OPP3	166	1.15
OPP2	133	1.06
OPP1	100	0.985

Note: Please refer to the AM/DM37x Datasheet for the latest OPP values.

AM37x VDD2 Operating Performance Points

OPP	L3_ICLK Frequency (MHz)	Voltage (V)
OPP100	200	1.15
OPP50	100	0.9735

Note: Please refer to the AM/DM37x Datasheet for the latest OPP values.

A TPS65023 power solution supports DVFS for OMAP35x or AM/DM37x by meeting the requirements shown in the table below.

Power IC Requirement for DVFS	Does TPS65023 based power solution implement the requirement?	How TPS65023 Power Module for the OMAP3EVM enables DVFS
Support all five DVFS voltage values (0.95V, 1V, 1.2V, 1.27V and 1.35V) defined for VDD_MPU	Yes. TPS65023 DCDC1 supports full voltage range and can adjust in 25mV increments	TPS65023 DCDC1 used to power VDD_MPU_IVA rail
Support all three DVFS voltage values (0.95V, 1V and 1.15V) defined for VDD_CORE	No. TPS65023 only supports a fixed voltage on DCDC2 for VDD_CORE.	TPS65023 DCDC2 fixed to 1.15V used to power VDD_CORE rail
I2C interface for setting output voltage to any of the values defined for DVFS	Yes. TPS65023 supports full speed I2C bus available for controlling voltage output for DCDC1 only.	I2C bus of TPS65023 connected to OMAP35x I2C bus

SmartReflex™ Adaptive Voltage Scaling (AVS)

AVS is a power management technique that can be used to refine system power consumption at a given OPP. The DVFS technique defines safe voltages for the OPPs so that all manufactured devices can meet the maximum frequency specifications for the OPPs. However, the silicon manufacturing process yields a distribution of devices, some (called Strong or Hot devices) of which can meet the frequency specifications at lower operating voltages than the conservative values defined by DVFS. SmartReflex™ AVS has been implemented by Texas Instruments to continuously adapt the operating voltage to the process properties of individual devices in order to maximize power savings for active scenarios. The OMAP35x and AM/DM37x integrates specialized hardware to enable SmartReflex AVS on VDD_MPU_IVA and VDD_CORE. This special hardware can be used to implement Class-3 or Class-2 SmartReflex.

• Class-2 SmartReflex: The special hardware monitors real-time performance; small software loop runs on ARM processor to change voltage whenever necessary.
• Class-3 SmartReflex: The special hardware has a dedicated hardware loop to dynamically monitor performance and adjust voltage without ARM processor intervention.

Equivalent power savings can be achieved with either implementation.

A TPS65023 power solution supports SmartReflex for OMAP35x and AM/DM37x by meeting the requirements shown in the table below. Please see Section 3.'5' for more implementation details.

Power IC Requirement for SmartReflex	Does TPS65023 based power solution implement the requirement?	How TPS65023 Power Module for the OMAP3EVM enables SmartReflex
High Speed (or Full Speed) I2C bus for setting output voltage	Yes. FS I2C bus available.	I2C connections present between TPS65023 and OMAP35x I2C bus
Voltage programmability in steps over the range 0.8V to 1.35V.	Yes only for VDD_MPU_IVA. Can scale the output voltage between 0.8V to 1.6V with voltage steps down to 25mV.	Makes use of this property of TPS65023 used to power VDD_MPU_IVA
(For Class-3 SmartReflex) Ability to effect voltage change with a single I2C register write	No. TPS65023 requires 2 I2C writes to change voltage and cannot support Class 3 SmartReflex	No support
(For Class-2 SmartReflex) Ability to effect voltage change with a sequence of one or more I2C register writes	Yes. Requires 2 register write sequence using DEFCORE register and GO bit.	TPS65023 I2C bus connected to OMAP35x general purpose I2C2 bus
Slew rate between 4mV/us and 16mV/us	Yes. TPS65023 supports multiple slew rates, including 7.2mV/us and 14.4mV/us selectable in DEFSLEW register.	Makes use of this property of TPS65023 used to power VDD_MPU_IVA

Static/Standby Leakage Management (SLM)

SLM is the combination of techniques utilized to achieve lowest power consumption during system idle time, when a system-on-chip (SoC) performs no useful processing. The OMAP35x and AM/DM37x supports various options for low power standby states that trade off level of power savings with speed of wakeup latency. The level of power savings during standby is determined by whether internal memories and logic are retained or powered down, whether clocks are on or off, and whether external voltage regulators are kept on or off.

Several SLM features are built into the OMAP35x architecture to enable low power standby modes. In addition, OMAP35x supports features for achieving further standby power savings by putting system components external to the OMAP SoC into lower power states. Notable among these, are control signals for gating external clock and power sources.

• SYS_CLKREQ is a signal used to gate the high frequency clock when it is not needed. The OMAP35x and AM/DM37x can be set up to automatically deassert the sys_clkreq in full-chip retention and/or off modes.
• SYS_OFF_MODE is a signal used to indicate to external voltage regulators when they can be shut down.

OMAP35x and AM/DM37x supports a standby mode called Off-mode, which is the lowest power state from which the device can wake up autonomously. In OMAP35x Off-mode, system state is saved in external memory that can be put into self-refresh mode, most of the SoC is off, but a small wakeup domain stays powered on and operational at 32kHz to monitor for wakeup events. The sys_clkreq is used to sequence an external clock source, while the sys_off_mode signal is used to sequence power during transitions into and out of the Off-mode. The ability to shut off most of the external voltage supplies in this Off-mode saves additional power dissipation in the voltage regulators. Alternatively to using the sys_off_mode pin, OMAP35x supports I2C commands for VDD_MPU_IVA and VDD_CORE sequencing during Off-mode transitions.

A TPS65023 power solution supports OMAP35x and AM/DM37x SLM by meeting the requirements shown in the table below.

Power IC Requirement for SLM	Does TPS65023 based power solution implement the requirement?	How TPS65023 Power Module for the OMAP3EVM enables SLM
Ability to gate high frequency clock source with IO signal for standby power savings	Yes. Can be taken care of in hardware with SYS_CLKREQ.	Not supported on power module
(For SLEEP mode) Ability to lower voltage on VDD_MPU_IVA power source to lowest OPP via I2C	Yes. Supports I2C register write to DEFCORE and GO bit to lower voltage to OPP1	Use I2C2 write to lower voltage on DCDC1 to OPP1.
(For SLEEP mode) Ability to lower voltage on VDD_CORE power source to lowest OPP via I2C	No. VDD_CORE voltage cannot be altered	DCDC2 voltage cannot be altered
(For OFF mode) Ability to turn off/on VDD_MPU_IVA power source with SYS_OFF_MODE signal or a single register write to the power IC over I2C	Yes. Supports I2C register write to REG_CTRL register of TPS65023 to turn off DCDC1 (VDD_MPU_IVA)	Use I2C2 write to disable DCDC1.
(For OFF mode) Ability to turn off/on VDD_CORE power source with SYS_OFF_MODE signal or a single register write to the power IC over I2C	Yes. Supports I2C register write to REG_CTRL register of TPS65023 to turn off DCDC2 (VDD_CORE)	Use I2C2 write to disable DCDC2

TPS65023 Design-In Considerations

Below is a block diagram of one example of a complete power solution using the TPS65023 devices to power OMAP35x (AM/DM37x are also applicable for this diagram). The rest of the section will detail each design consideration to tailor the power solution to your needs.

TPS65023 power solution block diagram

Reset

SYS_nRESPWRON rise time

The OMAP35x and AM/DM37x data sheet states that the maximum rise/fall time for SYS_nRESPWRON is 10ns

In order to meet this requirement, a push-pull output buffer is required, with rise/fall time of <10ns.

The TPS65023 RESPWRON output is open drain, and requires a buffer or gate with fast rise time to meet the OMAP35x and AM/DM37x requirement. If multiple reset sources are needed, you can use a AND gate as shown below to provide fast rise time for all reset sources.

SYS_nRESPWRON timing

Typical 32KHz oscillators on the market can have up to a 1 second maximum to stabilize. This poses a challenge in the power up sequencing in that the reset signal must be maintained low throughout this stabilization time in order to properly reset OMAP35x or AM/DM37x. You can achieve this lengthy reset time using the TRESPWRON input of TPS65023. Consult the TPS65023 data manual for detailed information. By connecting a capacitor to ground to this signal, you can adjust the delay time of the reset output RESPWRON.

For example, to achieve a 1sec reset delay, you can use a 10nF capacitor to ground. Please refer to the TPS65023 data sheet for more detailed information.

Clocks

Clock rise/fall time

OMAP35x clocks (both 32KHz and high frequency clocks) also have strict rise/fall requirements. Note the excerpts from the data manual below:

In order to meet these rise/fall times, a push-pull buffer is required to provide a faster edge on both clocks. Refer to the diagrams in sections 32KHz clock circuit and High Frequency Clock Circuit below.

Clock gating

When using an external oscillator for the high frequency clock, OMAP35x SYS_CLKREQ signal is used to request the high frequency clock. This signal can be used to gate the clock on power up while OMAP35x is going through its power up sequence.

Generally, the 32KHz oscillator will be powered off the 1.8V supply. This should be used as a condition before applying the 32KHz to the I/Os of OMAP35x or AM/DM37x.

32KHz clock circuit

If the 32KHz oscillator you choose exceeds the rise/fall time limit, a push-pull output buffer should be used to create a faster edge. Generally, the 32KHz oscillator will be powered off the 1.8V supply. This should be used as a gating condition before applying the 32KHz to the I/Os of OMAP35x or AM/DM37x. The TPS65023 provides an adequate 1.8V power good signal.

High Frequency Clock circuit

OMAP35x requires a high frequency clock for normal operation. OMAP35x accepts 2 different types of input clock sources:

• a crystal can be used in combination with the internal OMAP35x oscillator for frequencies 12, 13, 16.8, or 19.2MHz.

• a square oscillator can be used with the OMAP35x oscillator in bypass mode for frequencies 12, 13, 16.8, 19.2, 26, or 38.4MHz

When an external oscillator is used, it has strict rise/fall time restrictions of less than 2.5ns

In order to meet these requirements, a push-pull buffer is required before the clock input of OMAP35x.

Power Devices

A TPS65023 based power solution integrates many different power sources required to power up OMAP35x devices.

The TPS65023 features the following benefits to make it an ideal PMIC for OMAP35x or AM/DM37x:

• contains 3 DCDC converters and 2 LDOs with enough supply current for all OMAP35x family devices

• Each DCDC converter and the LDOs can be sequenced using external sense signals and enables.

• The second LDO inside TPS65023 can be used to power OMAP35x or AM/DM37x MMC rail. For power sensitive applications it is recommended to power the MMC rail off of a separate LDO to allow you to enable/disable the voltage separate from the PLL.

• Provides adjustable reset circuitry to control reset timing.

• provides adequate default voltages on power up

• provides I2C control of all power sources.

• provides voltage scaling and adequate voltage granularity to allow implementation of DVFS and SmartReflex AVS.

For applications requiring VDAC voltage, a separate LDO (TPS72118) is used which provides the proper 1.8V, 150mA maximum current. By connecting an OMAP35x or AM/DM37x GPIO, you can enable/disable this power source as the application needs it. An example schematic is below. If you are not using the video DAC on OMAP35x or AM/DM37x, you do not need to include this LDO in your design.

Note that while the voltage for VDD_MPU_IVA (connected to DCDC1) can be adjusted via I2C, the voltage for VDD_CORE (DCDC2) is fixed. The voltage level is fixed by means of external circuitry (see the TPS65023 documentation for details). To enable full performance, you must fix this voltage at the highest OPP (1.15V), however, if your application only requires lower performance levels, you can adjust your external circuitry to output a lower fixed voltage.

Sleep/Standby modes

As described above, the OMAP35x and AM/DM37x have many power management features that make it attractive in power sensitive applications. One aspect of this is the sleep/standby modes, which allow the device to enter very low power states while maintaining certain levels of functionality. The OMAP35x and AM/DM37x also have the ability to go into a deep sleep mode and still recognize wakeup events when needed.

With a TPS65023 power solution, you can implement a majority of these sleep/standby modes which will allow you to take advantage of the power savings of an OMAP35x or AM/DM37x solution. Many different sleep/standby modes exist, depending on which portions of OMAP35x need to be active for your application. With the TPS65023 solution, you have control over PLL and video DAC voltage, allowing you to completely shut off these supplies if needed. The MMC voltage can be controlled with an additional LDO if needed (The TPS65023 has only one enable for both LDOs, so MMC and PLL will both either be on or off at the same time) . You can also bring OMAP35x into some sleep modes by reducing voltage on VDD_MPU_IVA to the lowest retention voltage (0.95V). By implementing SmartReflex AVS, this voltage can potentially be lower, thus enabling further power savings. Using the PRCM (Power Reset Control Manager), you also can cut the power going to different domains on the device, including the domains for VDD_MPU_IVA and VDD_CORE. This brings you to near OFF mode power levels by reducing leakage power of OMAP35x or AM/DM37x.

The last step in OFF mode sequencing involves shutting down some voltage supplies. This step is supported by the TPS65023 power solution by using I2C writes to turn off and on the supplies. Note that only VDD_MPU_IVA voltage is adjustable (VDD_CORE is fixed). But you can still turn off these supplies to implement OFF mode.

Wakeup can then be achieved using I2C commands from the PRCM on OMAP35x. See the OMAP35x or AM/DM37x TRM for more information on Sleep and Wakeup sequencing.

Enabling Class 2 SmartReflex

The TPS65023 power solution only supports Class 2 SmartReflex. Class 3 SmartReflex is not supported with this solution. However, with Class 2, you can achieve similar power savings as you can with Class 3.

Class 2 SmartReflex

With a Class 2 SmartReflex implementation, the ARM processor in OMAP35x controls all of the functions of the TPS devices. You can use either OMAP35x I2C1, I2C2 or I2C3 to connect to the I2C port of the TPS65023. If possible, you should use a dedicated I2C bus between the processor and TPS65023. If you must share the bus with other peripherals, group the TPS65023 devices with peripherals which require only infrequent I2C activity. This will avoid long latencies during voltage changes.

To configure the TPS65023 devices for Class 2 SmartReflex, you should initialize them as follows

• Set slew rate to either 7.2 or 14.4mV/us in DEFSLEW register (for OMAP35x or AM/DM37x, slew rate must be between 4-16 mV/us)
• Control VDD_MPU_IVA voltage with DEFCORE register
• Use LDO_CTRL to adjust LDO2 down to 3.15 if needed for MMC (OMAP35x and AM/DM37x nominal voltage is 3.0V)
• After writing new voltage in DEFCORE, use GO bit in CON_CTRL2 register to change the voltage to the new value.

MMC Boot

OMAP35x processor has the ability to boot from many different sources. One possible boot configuration is to boot from MMC. This configuration requires that the MMC memory card is properly powered before ROM code executes (ie, on power on reset).

If MMC boot is a requirement in your application, you must ensure that VDDS_MMC1 (and VDDS_MMC1A if using 8-bit MMC data) is set for 3V operation at power up. It can later be turned off if necessary by your application.

In the TPS65023 power solution block diagram, the MMC voltage is connected to LDO2 of the TPS65023. The voltage will always be enabled on power up, because it shares an enable signal with LDO1 (the source for OMAP35x PLL voltage). If more control over MMC voltage is needed, you must use a discrete LDO to power OMAP35x MMC voltage, and use the processor's GPIOs to control its voltage and enable/disable signal. In the example schematic below, MMC1_EN and MMC1_VSET are connected directly to OMAP35x GPIOs. To ensure this power device is enabled and supplying 3.15V at power on reset, both MMC1_EN and MMC1_VSET must be high by default. To achieve this, we must choose GPIOs which default high at power up, or use an inverter where necessary.

Some applications may require MMC voltage sequencing to ensure 3.3V is valid before 1.8V. For this case, you can use two LDOs for each voltage to ensure proper sequencing, then enable/disable them using OMAP35x GPIOs.

Software/Hardware

You can find source code on the OMAP3 git tree that supports the TPS65023. Just go to the Linux OMAP kernel tree and search for "65023". Or you can just enable the TPS65023 driver in the latest OMAP3EVM kernel by entering menuconfig and choosing Device Drivers->Voltage and Current Regulator Support->TI TPS65023 Power regulators.

A TPS65023 power module for the OMAP3EVM exists in limited quantities. This power module can be used with the OMAP3EVM to evaluate the TPS65023 with OMAP35x or AM/DM37x. Please contact Andy Dykstra (dykstra@ti.com) for more information.