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Feature Comparison: ARM 926, 1136 and Cortex-A8
Key parameters of interest[edit]
The following table sumarrizes some of the key differences between the ARM 926, ARM 1136, Cortex-A8 and the Cortex-A9.
ARM926 | ARM1136 | Cortex-A8 | Cortex-A9 | |
Architecture Version | V5 | V6 | V7 | V7 |
Pipeline Type | in order,scalar | in order,scalar | in order,dual issue, superscalar | out-of-order, variable length, superscalar |
Pipeline Stages | 5 | 8 | 13 | 8 |
ISA Efficiency (DMIPS/MHz) | 1.07 | 1.18 | 2.01 | 2.5 |
MMU | Yes | Yes | Yes | Yes |
TLB | 8 entry unified | 2 uTLB and LB | 2x32 full associativity | 4 element fully associative +
2x32 two-way associative |
Core to L1 Interface | 32 bit | 64 bit | 64 bit -- NEON 128 bit | 64 bit -- NEON 128 bit |
L1 $ Set associativity | 4 | 4 | 4 | 4 |
Line Length | 32 Bytes | 32 Bytes | 64 Bytes | 32 Bytes |
Tightly coupled memory | Yes | Yes | No | No |
Integrated L2 | No | No | Yes | Yes |
Cache Model | VIVT | VIPT | L1 - VIPT
L2 - PIPT |
Instruction - VIPT
Data -PIPT |
Branch Prediction | No | 128 Entry BTB | 512 Entry BTB | 2 way x 256 BTAC |
General Coprocessor Interface | Yes | Yes | No | No |
External Interfaces | 2 AHB 2.0 | 5 AHB 2.5 – 3 x 64 bit, 2 x 32 bit | 1 AXI – 64/128 | 2 AXI 64 bit |
Trustzone support | No | No | Yes | Yes |
Non Cacheable Fill Buffer | 4 word | 8 word | 16 word | 2 - 8 word |
Java support | Jazelle DBX | Jazelle DBX | Jazelle RCT | Jazelle DBX |
Floating Point Media | No (coprocessor available, VFP9) | VFP11 attached, V6 Integer SIMD | VFP Lite and NEON SIMD | VFPv3 and NEON SIMD |
Per-Cycle Multiply-accumulate
throughput (fixed point) |
1 x 32 bit
1 x 16 bit |
1 x 32 bit
2 x 16 bit Float: 2 x 32 bit |
2 x 32 bit 4 x16 bit
8 x 8 bit |
2 x 32 bit
8 x 8 bit |