Understanding Trace Timing

Understanding Trace Timing

All timing and pipeline stall data is accumulated in E5 of the pipeline, see Pipeline Flattener for details. The Trace Display's "Trace Status" column is used to interpret the "Cycle" column data per the following table:

Trace Status	Timing Interpretation
Pipeline stall	The delta cycles between the current sample and next sample are caused by a stall.
Execution continued	A multi-cycle instruction was stalled, the stall is complete and the delta cycles between the current sample and next reflect the normal pipeline advanced (no stall).
No Pipeline stall AND No Execution continued	The delta time between the current sample and the next will reflect the normal pipeline advance caused by instruction execution (no stall). Cycles that reflect a pipeline advance are aligned with the PC.

The following DVT screen shot shows how the timing data is related to the execution pipeline.

Event Trace Stall or Last Stall Standing Analysis: 

 The "Stall Cycle Data binary" column is a binary representation, selected from one of four stall trace event groups. In this case event group 1 ( bit 1 - decimal 2) is programmed for any L1D stall event, which is why we know the particular Pipeline Stall in the example is caused by a L1D stall event. Only stalls associated with the selected event group are reported.