Pipeline Flattener

Pipeline Flattener

The Pipeline Flattener functions as the front end for the AET and Trace modules. As instructions are executed, data required for trace and triggering are available from different pipeline stages. Since the trace data has to be collected from different pipeline stages on different cycles, this data must be aligned prior to being driven to the AET and Trace blocks. The following table shows the relationship between instruction execution, availability of PC and memory access data during different pipeline stages and the alignment of that data for AET and Trace consumption. For details on the c64+ pipeline see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide.

The following table shows a snapshot in time of the pipeline stages and what is exported to the AET and Trace modules.

Cycle	1	2	3	4	5	6	7	8	9
Pipeline Stage	E1	E2	E3	E4	E5	E5+1
PC	PC9	PC8	PC7	PC6	PC5	PC4	PC3	PC2	PC1
CPU Memory Cycles		Addr8 Ctl8 Wdata8	Addr7 Ctl7 Wdata7	Addr6 Ctl6 Wdata6	Addr5 Ctl5 Wdata5	Addr4 Ctl4 Wdata4	Addr3 Ctl3 Wdata3	Addr2 Ctl2 Wdata2	Addr1 Ctl1 Wdata1
Memory System Response					Rdata5	Rdata4	Rdata3	Rdata2	Rdata1
Output to AET				PC6 Addr6 Ctl6	PC5 Addr5 Ctl5	PC4 Addr4 Ctl4 Wdata4 Rdata4	PC3 Addr3 Ctl3 Wdata3 Rdata3	PC2 Addr2 Ctl2 Wdata2 Rdata2	PC1 Addr1 Ctl1 Wdata1 Rdata1
Output to Trace						PC4 Addr4 Ctl4 Wdata4 Rdata4	PC3 Addr3 Ctl3 Wdata3 Rdata3	PC2 Addr2 Ctl2 Wdata2 Rdata2	PC1 Addr1 Ctl1 Wdata1 Rdata1
Timing and Stall info accumulated in E5 for the entire pipeline					E5-PC5 E4-PC6 E3-PC7 E2-PC8 E1-PC9	E5-PC4 E4-PC5 E3-PC6 E2-PC7 E1-PC8	E5-PC3 E4-PC4 E3-PC5 E2-PC6 E1-PC7	E5-PC2 E4-PC3 E3-PC4 E2-PC5 E1-PC6

Notes:

• Output to AET occurs in E4 with PC, data address and data control, and completes in E5+1 with both read and write data.
• Output to Trace occurs in cycle E5+1 with PC, data address, data control, read and write data, and timing.
• Timing & Stall data are not flattened, but are accumulated during pipeline stage E5. See Understanding Trace Timing for more details on using Trace Status to interpret the Trace Display's Cycle column and an example of how to apply the rules to the Trace Display.