TraceDeviceFeatures

What's in the device to facilitate trace

• Non-intrusive export of trace data streams:

- PC and SPLOOP addresses(C64+ cores only)

- Timing data correlated to all other streams

- Memory read (core only - address, data & access size)

- Memory write (core only - address, data & access size)

- Events (replaces Memory read/write streams when enabled)

- PC, Timing and Memory read/write streams can be active simultaneously or PC, Timing and Event streams can be active simultaneously

• Trace data types - mutually exclusive of each other

- Standard Trace

=> PC, memory read and writes, and timing

- Event Trace

=> Stall events(CPU, L1P & L1D), Memory system events(L1D, L2 & External), or device specific external events (interrupts, exceptions, error detection, ...)

=> PC and Timing

• Advance Event Triggering(AET) is used to select the Trace Trigger actions, type and what to trace:

- Trace types (Standard or Event)

- Trigger actions (on, start, end, range, end all ...) - See Trace Jobs for details on trigger types.

- Trigger types (PC, Memory or Event)

- For Standard Trace select what to trace (PC, Timing, and Memory access)

- For Event trace what to trace is automatically selected (PC, Timing and Event selected)

- See Advanced Event Triggering (AET) Logic for details on how the silicon trigger builders work.

• Pipeline Flattener aligns memory accesses to PCs

- With unprotected pipelines (c6x) memory accesses occur in parallel with subsequent instructions.

- The Pipeline Flattener aligns the memory access address and data with the PC of the originating instruction.

- See Timing Stream Limitations section for stall timing details.

• Trace data compression

- High trace compression rates (~5 million samples/1MByte of trace data)

• Trace data export

- Off-chip export collected by an XDS560 Trace Pod

- On-chip export to Embedded Trace Buffer(ETB)

=> Any XDS may be used

=> ETB provides a very limited trace buffer size

=> Once a c64x+ core's ETB is selected to receive trace data, it's trace export to the pins is disabled

=> In multi-core c64x+ devices (where each mega-module contains a dedicated ETB) multiple cores can export trace to the ETBs simultaneously, while only a single core can export trace data to the pins (for collection by an XDS).

=> ETBLib and DSPTraceLib projects available for application configuration at CtoolsLib

• Abbreviation Key

AET - Advance Event Trace

DTF - DSP Trace Formatter

ETB - Embedded Trace Buffer

PF - Pipeline Flattener