Setting up AM35x SDRC registers

Introduction

The following information describes how to set the SDRC registers in the AM35x SDRC module depending on the mDDR or DDR2 memory that you are using. Only 32-bit configurations are addressed in this wiki.

PAD_CONFIG registers

Almost all SDRC signals are enabled by default for DDR functionality in the pin muxing registers of AM35x. The only exception is the SDRC_CKE0, which is configured to safe mode by default. You must configure this to mode 0 to enable proper functionality of this signal.

CONTROL_PADCONF_SDRC_CKE0 (0x48002260) - set bits [18:16] to 0.

SDRAM General Configuration Registers

• SDRAM_CONFIG (@0x6D000008)- The values in this register will depend a lot on your memory configuration. Here are some tips to configure each value:
  
  • REG_SDRAM_TYPE - LPDDR1 (mDDR) = 1, DDR2 = 2
  • REG_IBANK_POS - This register sets up the internal bank position. Please see "SDRAM Address Mapping" section of the TRM for more information
  • REG_DDR_TERM - DDR2 termination resistor value. This is typically set to 0 for no termination. Refer to ODT support presentation for more information on using ODT.
  • REG_DDR2_DDQS - DDR2 differential DQS enable. Set to 0 when using LPDDR (mDDR) for single ended DQS. Set to 1 when using DDR2 for differential DQS.
  • REG_DDR_DISABLE_DLL - Set to 0 for normal operation
  • REG_SDRAM_DRIVE -SDRAM drive strength. For LPDDR1, typically you would set this to 1 for weak drive strength. Some boards with LPDDR may require full drive strength depending on board size and trace impedances. For DDR2, set to 0 for full drive strength.
  • REG_NARROW_MODE - SDRAM data bus width. Set to 0 for 32-bit and set to 1 for 16-bit. All other values are reserved.
  • REG_CL - CAS Latency. The value of this field defines the CAS latency to be used when accessing connected SDRAM devices. This value should come directly from the DDR datasheet. Value of 2, 3, 5, and 6 (CAS latency of 2, 3, 1.5, and 2.5) are supported for LPDDR1. Value of 2, 3, 4, 5, and 6 (CAS latency of 2, 3, 4, 5, and 6) are supported for DDR2. All other values are reserved. Ensure that the value in this register agrees with the value in READ_LATENCY in DDR_PHY_CTRL_1 register.
  • REG_ROWSIZE - This field is only used when reg_ibank_pos field in SDRAM Configuration register is set to 1, 2, or 3. Should be set to the number of row address bits defined in the DDR datasheet.

# of row bits	REG_ROWSIZE Value
9	0
10	1
11	2
12	3
13	4
14	5
15	6
16	7

• • REG_IBANK - Internal Bank setup. Defines number of banks inside connected SDRAM devices. Set to 0 for 1 bank, set to 1 for 2 banks, set to 2 for 4 banks, and set to 3 for 8 banks. All other values are reserved.
  • REG_EBANK - External chip select setup. Defines whether SDRAM accesses will use 1 or 2 chip select lines. Set to 0 to use sdrc_cs0 only. Set to 1 to use both sdrc_cs0 and sdrc_cs1.
  • REG_PAGESIZE - Page Size. Defines the internal page size of connected SDRAM devices. Should be set to the number of column address bits defined in the DDR datasheet

# of column address bits	REG_PAGESIZE Value
8 (256-word page)	0
9 (512-word page)	1
10 (1024-word page)	2
11 (2048-word page)	3

DDR PHY Control Registers

• DDR_PHY_CTRL_1 (@0x6D0000E4)
  • TESTIN_LB_CK_SELECT - Set to 0.
  • CONFIG_VTP_DYNAMIC_UPDATE - This bit controls the VTP (Voltage, Temperature, Process) Compensation for the DDR I/Os. The VTP Compensation needs to be calibrated after each DDR PHY reset. Here is the sequence you should follow to properly calibrate the I/Os.
    • Give PHY RST (which in turn also gives reset to vtp controller).
      • To give this reset, set bit REG_RESET_PHY to 1 in IODFT_TLGC register (reg. addr. 0x6D00 0060) of EMIF module
      • Poll till REG_RESET_PHY flag gets cleared. This makes sure that reset to phy got deasserted.
    • Set CONFIG_VTP_DYNAMIC_UPDATE = 1.
      • Set field CONFIG_VTP_DYNAMIC_UPDATE in DDR_PHY_CTRL_1 register (reg. addr. 0x6D00 00E4) of EMIF module
      • Set field CONFIG_VTP_DYNAMIC_UPDATE in DDR_PHY_CTRL_1_SHDW register (reg. addr. 0x6D00 00E8) of EMIF module
    • Poll for assertion of VTP_READY flag from the VTP controller.
      • VTP_READY status can be read from VTP_READY bit in register CONTROL_DEVCONF3 (reg. addr. 0x4800 2584) in system control module
    • Clear CONFIG_VTP_DYNAMIC_UPDATE to 0 in both DDR_PHY_CTRL_1 and DDR_PHY_CTRL_1_SHDW register. (Keeping CONFIG_VTP_DYNAMIC_UPDATE set to 1 will consume more power and should not be necessary for most applications).
    • Continue to initialize the rest of the EMIF.
  • CONFIG_DLL_MODE - Set to 0.
  • DR_16B_MODE_PWRSAVE - Set to 0.
  • CONFIG_EXT_STRBEN - use 0 (Internal Strobe) for DDR2; use 1 (External Strobe) for LPDDR1
  • CONFIG_PWRDN_DISABLE - this bit controls the power to the receive IO buffer. Setting the bit to 0 will conserve power by shutting down the buffer when no read accesses are occurring. Alternatively, set it to 1 to keep power to the buffers enabled.
  • READ_LATENCY - This value should be set to the following

(CAS latency + 1) >= READ_LATENCY >= CAS latency

It defines the read latency for read data from the DDR. Typically the max value is used (ie, CAS latency + 1), but better performance can be achieved with the mimimum value. Ensure that the value in this register agrees with the value in REG_CL in SDRAM_CONFIG register.

• DDR_PHY_CTRL_2 (@6D0000EC) - This register should be set to 0x00000000
  • CONFIG_RX_DLL_BYPASS - Set to 0.
  • CONFIG_TX_STRB_DATA_ALIGN - Set to 0.

To configure the DDR PHY, setup DDR_PHY_CTRL_1, DDR_PHY_CTRL_1_SHDW, and DDR_PHY_CTRL_2 to the appropriate values, and then reset the DDR PHY setting IODFT_TLGC.REG_RESET_PHY (bit 10 of address 0x6D000060) to 1. Wait for STATUS.REG_PHY_DLL_READY (bit 2 of address 0x6D000004) to be set to 1 to ensure PHY is ready for normal operation.

AC timing registers

• SDRAM_TIM_1, SDRAM_TIM_2, and SDRAM_TIM_3

This spreadsheet will help you determine the optimal values for the AC timing registers:

AM35x DDR Calculation tool (.zip)

The values in yellow need to be changed based on the datasheet values for your memory. Ensure that you enter the correct values for the speed grade of your device. The tCK value should represent the speed at which you will be running the device (not necessarily the minimum value in the datasheet). The register values for the AM35x AC timing registers will be calculated based on these inputs. For more conservative values, you can back off these optimal values (ie, increase each value by 1 or 2).

Setting Refresh rate

• SDRAM_REF_CTRL - To set the refresh rate, get the Periodic Refresh interval tREFI from the memory datasheet. Note that this value is typcially in the us range. Some datasheets may refer to a "Refresh Interval time" in the millisecond range (64ms, for example), however, this value needs to be divided by the number of refresh cycles needed (typically 8000).
  
  • REG_REFRESH_RATE - the number of clock cycles required to cause a refresh interval of 7.8 us or 15.7 us for the appropriate SDRAM used. This field is not byte writable, i.e., all 16 bits of this field need to be written simultaneously. Here are some examples
• For 166 MHz memory system with 15.7us refresh rate: 166 * 15.7 = 2606.2 or 0xA2E
• For 166 MHz memory system with 7.8us refresh rate: 166 * 7.8us = 1294.8 or 0x50E

Power Management Control Register

This register is typically set to 0x80000000, which enables smart-idle mode and disables automatic power management. If you want to use the automatic power management, you would set REG_LP_MODE to the power state that you want to enter after a timeout value setup in REG_PM_TIM.

For more details on these registers, please refer to the AM35x TRM.

• PWR_MGMT_CTRL (@0x6D000038)
  • REG_IDLEMODE - Power-Idle IP Generic mode. 0 = Force Idle Mode; 1 = No-Idle mode; 2 = Smart Idle.
  • REG_DPD_EN - Deep Power Down enable (setting this to 1 overides REG_LP_MODE)
  • REG_LP_MODE - Auto Power management enable. 0 = disable auto pwr mgmt; 1 = clock stop; 2 = Self Refresh; 3 = Power-Down 
  • REG_PM_TIM - Power Management Timer.  Number of clock cycles to wait after EMIF is idle before going into power saving mode.

Shadow Registers

The AM35x devices support smart idle mode for power conservation. Upon returning from smart idle mode, the shadow registers are loaded into the SDRC registers.

• SDRAM_REF_CTRL_SHDW - Refresh Control Shadow Register. Ensure that this register is written with the same value as SDRAM_REF_CTRL register.
• SDRAM_TIM_1_SHDW - SDRAM Timing 1 Shadow Register. Ensure that this register is written with the same value as SDRAM_TIM_1 register.
• SDRAM_TIM_2_SHDW - SDRAM Timing 2 Shadow Register. Ensure that this register is written with the same value as SDRAM_TIM_2 register.
• SDRAM_TIM_3_SHDW - SDRAM Timing 3 Shadow Register. Ensure that this register is written with the same value as SDRAM_TIM_3 register.
• PWR_MGMT_CTRL_SHDW - Power Management Control Shadow Register. Ensure that this register is written with the same value as PWR_MGMT_CTRL register.
• DDR_PHY_CTRL_1_SHDW - DDR PHY Control 1 Shadow Register. Ensure that this register is written with the same value as DDR_PHY_CTRL_1.

System Control Module Registers

There are a few pertinent registers in the System Control Module (SCM) that affect DDR operation

• CONTROL_DEVCONF3 (@0x48002584) - Typically, this register stays at its default value except for DDR_CMOSEN. Typical values are 0x00008600 for DDR2, and 0x00009600 for mDDR. Below are the details for each bit.

• • DDRPHY_CLK_EN - Set this bit to 1 for normal operation. Set to 0 to turn off clocks to PHY to save power.
  • EMIF4A_FCLKEN - Set this to 0 for normal operation
  • VTP_PWRSAVE - this is typically set to 0.
  • DDR_CMOSEN - Set to 0 for DDR2. Set to 1 for mDDR
  • VTP_DRVSTRENGTH - Should be left at the default 0x3
  • DDR_VREF_EN - Set to 0 to choose external reference for VREF. Consult the layout guidelines in the datasheet for more information on setting up this reference voltage externally.
  • DDR_VREF_TAP - keep this at the default value of 0. Only used when an internal reference is selected
  • VTP_READY - this is a read-only bit
  • DDR_CONFIG_TERMOFF - This controls the parallel termination during a non-read cycle for all SDRC data signals. Set to 0 for normal operation. Other settings are not typically necessary and will result in increased power consumption. Refer to ODT support presentation for more information on using ODT.
  • DDR_CONFIG_TERMON - This controls the parallel termination during a read cycle for all SDRC data signals. Set to 0 for normal operation. Other settings are not typically necessary and will result in increased power consumption. Refer to ODT support presentation for more information on using ODT.

Initialization Sequence

• The best source for proper initialization sequence is the xloader source code, which can be found from TI'sTI's Linux Software Development Kit in board/am3517evm/am3517evm.c.
• In general, here are the steps to take:

1. Setup DDR PHY control registers
2. Reset the PHY (using IODFT_TLGC) and wait till complete
3. Perform a VTP calibrate
4. Configure EMIF
   1. Setup timing registers (SDRAM_TIM_xxx)
   2. Setup Power control reg (PWR_MGMT_CTRL)
   3. Setup refresh rate (SDRAM_REF_CTRL)
   4. Setup SDRAM configuration register (SDRAM_CONFIG)

When you write to SDRAM_CONFIG, this kicks off the hardware sequence which initializes the DDR interface (the details are described in the TRM).

Step 3 is not in the linux code because this was a recent enhancement to our DDR initialization sequence (and is another reason why it isn't in the TRM yet). The VTP calibration sequence performs a calibration on the DDR I/Os. A lot of designs may work without this calibration (as in the case of the EVM), but you will likely see more robust performance with the calibration.

More Tips

• AM35x can only handle a max of 1GByte of memory over 2 chip selects. Furthermore, it is recommended that you only present 2 loads to the AM35x SDRC signals. Some memories increase capacity by stacking dies in their packages. For example, a package with 2 dies presents 2 loads to the SDRC signals. Ensure that your configuration does not present more than 2 loads to the AM35x SDRC signals

8Gb = 1GByte
4Gb = 512MByte
2Gb = 256MByte
1Gb = 128MByte