SD-MMC Usage Notes on AM35x

Introduction

This wiki explains how to design with the SD-MMC interface on the AM35x processors. Please refer to the OMAP35x and AM37x SD-MMC Usage Notes wiki if you want information for those devices.

Allowable Voltages on the MMC interfaces

MMC1-3 voltages are dictated by the I/O voltage of the AM35x VDDSHV. VDDSHV defines the I/O voltage for the whole device (except DDR and a few other interfaces), and can be set to 1.8V or 3.3V. This voltage is static and cannot be changed during normal operation.

Using MMC1 and MMC3

MMC1 and MMC3 can support either 1.8V or 3.3V I/Os, depending on VDDSHV. There is no internal transceiver present on MMC1 or MMC3. They were designed to connect directly to cards/peripherals with the same voltage as VDDSHV. In other words, it was not intended that they connect to a transceiver for voltage translation and so they do not have direction signals. Whenever possible, it is best to use cards/peripherals on MMC1 and MMC3 that match the supply voltage VDDSHV, and to use MMC2 if voltage translation is necessary.

If it is not possible to match the card/peripheral to the VDDSHV supply, it is possible to use an external transceiver with auto sensing direction capabilities. There are several possible solutions, such as TXS0206 or TXS0108E. It is recommended that you only use this configuration if you are able to place the processor, transceiver, and MMC/SD device close together with short trace lengths. Long trace lengths can introduce large capacitive loading and affect functionality. Also, high speed MMCSD (ie, 48MHz) is best achieved without a transceiver.

The ROM code supports booting from MMC1 (not MMC3). It can boot from a 1.8V or 3.3V device, as this is dictated by the I/O voltage of the AM35x, VDDSHV.

When using MMC1 or MMC3, ensure that all PADCONF registers associated with MMC1/3 signals have INPUTENABLE=1. Even MMC1_CLK (MMC3_CLK) needs input enabled, as this clock is reused from the pin by the module to retime incoming data.

Using MMC2

MMC2, with its direction control signals and CLKIN, is best suited for designs which need relaxed design constraints (large boards or long traces). By default MMC2 is configured to utilize the mmc2_clkin input (CONTROL_DEVCONF1.MMCSDIO2ADPCLKISEL=0), however, please make sure that this bit is set correctly.

MMC2 operates at the voltage level of VDDSHV. However, it also provides additional signals (mmc2_clkin and direction control signals) permitting it to control a bi-directional transceiver (this transceiver can also optionally support level shifting necessary to support dual-voltage MMC/SD cards) . Note that when you use MMC2 with the direction signals, you are limited to 4-bit data since some of the direction signals are muxed with the upper data bits. For example, you can connect it to the SN74AVCA406L which allows you to connect to SD/MMC cards/peripherals that are not the same voltage as VDDSHV. The MMC2 interface compensates for signaling delay by using mmc2_clkin. So you can take mmc2_clk, run it through the level shifter (e.g. to 3.3V), take that output and run it back through the level shifter (back to 1.8V) and input that signal to mmc2_clkin. The SN74AVCA406L actually has a pin dedicated to that purpose. You simply connect the CLK-f pin of the SN74AVCA406L to the mmc2_clkin pin of the AM35x. The MMC2 peripheral can now accurately account for the delay that occurs (both in the MMC card getting the 3.3V clock and in the peripheral getting back the delayed data from the MMC card).

Auto direction sensing tranceivers, such as the TXS0206 or TXS0108E, are popular devices used for MMC voltage translation and do not require direction signals. These have been used successfully by customers on MMC2. In these cases, the MMC2_CLKIN signal was not used, and CONTROL_DEVCONF1.MMCSDIO2ADPCLKISEL=1 (ie, internal loopback). It is recommended that you only use this configuration if you are able to place the processor, transeiver, and MMC/SD device close together with short trace lengths. Long trace lengths can introduce large capacitive loading and affect functionality.

The AM35x ROM assumes the use of MMC2_CLKIN (ie, the boot ROM uses CONTROL_DEVCONF.MMCSDIO2ADPCLKISEL=0). This means that if you want to boot from MMC2, you must supply a clock on MMC2_CLKIN, and so you should use an external transceiver such as the SN74AVCA406L. Attempting to simply loopback MMC2_CLK to MMC2_CLKIN on your board is not recommended. You should use the feedback clock signal from the external transceiver when possible.

Also note that mmc2_dir_dat1 signal is meant for the direction signal of dat1 and dat3. This means some glue logic (or external GPIO) might be necessary if you need both "dir_dat1" and "dir_dat3" signal being sent to the level shifter. Note you can "double" the driven current (buffer strength) on "mmc2_dir_dat1" signal from the default 4mA to 8mA.

In this respect mmc2_dir_dat0 only control the direction signal for dat0. Same for mmc2_dir_dat2 which only control the direction signal for dat2.

Other considerations

• To support managed NANDs (e.g. eMMC, moviNAND), the device must be able to respond properly to a CMD1, ARG=0 command. The ROM sends this command to query the device's voltage capabilities. Since most mangaged NANDs operate with two voltages (typcially, 1.8V for I/O, 3.3V for core), the response differs among different manufacturers. The ROM will only tell the managed NAND device that it will operate at 3.3V. If the device switches off in response to a CMD1, ARG=0, or if the device cannot handle operation at 3.0V, then the ROM will not be compatible with it.
• PBIAS_LITE functionality is not included in the AM35x devices, as it is with OMAP35x and AM37x.
• The I/O pads have very strong drive strength. It's recommended to use series resistors (start around 30 ohms and tune to your board design) to dampen over/undershoots. At a minimum you should be sure to include the resistor on the clock pin as it has the potential to create the most issues. The resistor should be placed close to the AM35x.