OMAP-L138 Hardware Design Guide

Hardware Design Timeline →

Constructing the Block Diagram

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Selecting the Boot Mode

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Confirming Pin Multiplexing Compatibility

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Confirming Electrical and Timing Compatibility

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Designing the Power Subsystem

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Designing the Clocking Subsystem

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Floorplanning the PCB

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Creating the Schematics

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Laying out the PCB

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Testing / Debugging

 

Introduction

Welcome to the OMAP-L138/C6748/AM1808 Hardware Design Guide.  The purpose of this guide is to walk hardware designers through the various stages of designing a board around OMAP-L138/C6748/AM1808 .  The guide follows the structure shown in the Hardware Design Timeline above.  Each design stage in the Timeline links to a collection of useful documentation, application notes, and design recommendations pertaining to that stage.  Using this Guide, hardware designers can efficiently locate the resources they need at every step in the board design flow.

Constructing the Block Diagram

The first step in designing the hardware platform is to create a detailed block diagram.  The block diagram should contain all major system ICs and illustrate which I/O ports are used for device interconnection.  Below is a collection of resources to aid in the Block Diagram creation process.

• Select from a list of complementary devices to attach to OMAP-L138/C6748/AM1808 in your system
  • OMAP-L138/C6748/AM1808 Complementary IC Wiki

Selecting the Boot Mode

The block diagram should also indicate which interface will be used for booting the OMAP-L138/C6748/AM1808 .  Upon coming out of reset, the processor must boot up by loading its application code from external storage. The application code can be loaded from a ROM or can be downloaded from another processor in the system.  The processor contains a primary bootloader burned into its internal ROM which is run by the processor after coming out of reset. This primary bootloader performs some critical initial tasks and then loads application code from the external interface specified by the processor boot configuration pins. See the below information for selecting an implementing the right boot mode for your system.

• Read the following document to learn about the possible boot options
  • OMAP-L138 Bootloader Application Report
  • C6748 Bootloader Application Report
  • AM1808 Bootloader Application Report
• Understand the details of the boot process and view frequently asked questions
  • OMAP-L138/C6748/AM1808 Bootloader
• The following Wiki provides example code and walk through the process of creating, flashing, and booting programs on the EVM:
  • Boot Images for OMAP-L138/C6748/AM1808
• See the following articles on selecting the right boot mode for your application:
  • Boot times for host boot modes
  • Comparison of various boot media
  • List of NANDs devices supported by TI ROM Bootloaders (RBLs)
  • Comparison of managed NAND vs raw NAND
  • NAND Boot FAQ
  • NOR boot flash compatibility
    
    • For booting, any NOR flash should be compatible as long as it is connected properly (CS2 of the EMIF, address and data lines done correctly for specified bus width, etc.).
      
  • SPI boot flash compatibility
    • SPI flash can be used for booting provided it uses 24-bit addressing and supports the read command 0x3.
• Key Boot Considerations:
  • It is recommended to include population options for other boot modes to aid in development
    
  • Boot pins have other functions after reset. Make sure your board design takes this into account when choosing pullup/down resistors for the boot pins.

Confirming Pin Multiplexing Compatibility

The processor uses internal pin multiplexing to allow for maximum functionality in the smallest and lowest cost package.  Due to this pin multiplexing, not all processor interfaces are always available simultaneously.See the Terminal Functions section of the datasheet for complete details on the pin multiplexing.  Also see the below information for tools and tips related to pin multiplexing.

• Use the following tool to verify that the processor pin multiplexing is compatible with you system block diagram
  • OMAP-L138 and C6748 Pin Multiplexing Tool
  • AM1808 Pin Multiplexing Tool

Confirming Electrical and Timing Compatibility

A key step in the hardware design before beginning schematic capture is to confirm both DC and AC electrical compatibility between the processor and the other ICs connected to it.  See the below collection of information to aid in confirming the system's electrical compatibility

• Checking I/O voltage compatibility between ICs
• Checking I/O timing compatibility between ICs
• Using IBIS Models for Timing Analysis
• Note: TI provides PCB layout specifications in the device datasheets for the following interfaces, eliminating the need to perform electrical analysis:
  • DDR
  • SATA
  • USB

Designing the Power Subsystem

Once the block diagram has been validated for pin multiplexing, electrical, and timing compatibility, the power sub-system can be designed. See the below resources on estimating processor power consumption and designing a matching power subsystem.

• Use the Power Spreadsheet to estimate processor power in a custom application
  • OMAP-L138 Power Consumption Summary (Power Spreadsheet)
  • C6748 Power Consumption Summary (Power Spreadsheet)
  • AM1808 Power Consumption Summary (Power Spreadsheet)
• Reuse or modify one of the existing power supply reference designs
  • OMAP-L138 Power Reference Designs
  • C6748 Power Reference Designs
  • AM1808 Power Reference Designs
• Key Considerations for designing the Power Subsystem:
  • Make sure to follow the supply sequencing requirements listed in the datasheet
  • Make sure to properly filter the PLL power supply according to the recommendations listed in the datasheet
  • A 1.8V regulator is still required even if all I/Os are configured to 3.3V
• For supporting different voltage operating points, the following rules must be followed:
  • CVDD should not exceed RVDD
  • RVDD should not drop below 1.2V regardless of CVDD voltage or operating point
  • RTC_CVDD may be tied to CVDD if RTC peripheral is unused, regardless of CVDD voltage
  • Other 1.2V supplies (PLL0/1_VDDA, SATA_VDD, USB_CVDD, USB0_VDDA12), if used, should be tied to a separate 1.2V supply if CVDD operating point is not at 1.2V. Otherwise they may share the same supply.

Designing the Clocking Subsystem

In addition to the power subsystem, the clocking subsystem needs to be designed to provide appropriate clocks to all ICs in the system. These clocks can be created by pairing crystals with internal oscillators within the system ICs, or they can be created by a separate clock generator. See the below information on designing the clocking subsystem for your design.

• Key Considerations for designing the Clocking Subsystem:
  • A 100MHz reference clock is required by the processor when using SATA port.

Floorplanning the PCB

Before beginning schematic capture, it is recommended to floor plan the system PCB to determine the interconnect distances between the various system ICs. See the below information on floor planning your PCB.

• TBD: Why and How to floor plan your PCB before starting schematic capture

Creating the Schematics

At this point in the design, it is time to start capturing the schematics. See the below collection of information to aid you in creating the schematics for your design.

• It is often helpful to refer to example schematics throughout the schematic capture process:
  • Logic PD OMAP-L138 / C6748 EVM Schematics
  • Logic PD AM1808 EVM Schematics

• Make sure to use the canned schematics in the datasheet for the following interfaces:
  • DDR
  • SATA
• Below is a collection of articles showing example connections of various components to the processor
  • Using SPI Chip Select Pin on C674x/OMAP-L1x
  • Connecting NOR Flash to C674x/OMAP-L1x
  • Connecting NAND Flash to C674x/OMAP-L1x
    • Programming Asynchronous EMIF configuration for interfacing with NAND
  • LCD Panel Connections LCD_connectivity LCD Panel Connections(applies to these chips as well)
• During and after schematic capture, check your design against the processor schematic checklist:
  • OMAP-L13x / C674x / AM1x Schematic Review Checklist
  • TMS320C674x/OMAP-L1x USB Compliance Checklist
• Below is a link to the IBIS Simulation Models to aid in the design of the device interconnects:
  • OMAP-L138 IBIS Models.
  • C6748 IBIS Models.
  • AM1808 IBIS Models.
• Below is a link for selecting a placing decoupling capacitors in a BGA design
• Decoupling Capacitor Selection and Placement for BGAs

• Key Considerations for Capturing Schematics:
  • SDRAM (and other) output clocks are internally looped back
  • Don’t forget to install a JTAG connection
  • JTAG: Make sure to use the RTCK pin

Laying out the PCB

After completing schematic capture, see the below information on laying out the PCB for your system:

• It is often helpful to refer to an example layout when designing a custom PCB:
  • Logic PD OMAP-L138 / C6748 EVM Layout
  • Logic PD AM1808 EVM Layout

• Make sure to follow the Layout Specifications for the following Critical Interfaces:
  • USB 2.0 Board Design and Layout Guidelines
  • DDR - See Datasheet
  • SATA - See datasheet

• General Information Articles:
  • Understanding TI's PCB Routing Rule-Based DDR Timing Specification
  • BGA/PCB Design for BGAs
  • Decoupling Capacitor Selection and Placement for BGAs

OMAP-L138 Complementary Products

This section serves as a repository of complimentary Devices that can be paired with the OMAP-L138 SoC devices when integrating the device into a system. The Complementary Products listed on the wiki serve a wide range of functions such as:

• Providing basic support functions for the SoC (power, clocking, etc.)
• Expanding the interface options beyond the on-chip peripherals
• Creating the link between the digital domains on the SoC to the system's analog/physical domains

Click here for Wiki article on Complimentary products

Testing/Debugging

Debugging Tools

Once your custom PCB has been produced and assembled, refer to the below information on bringing-up and debugging the system.

• See the below GEL Files that aid in configuring your design during debug/development
  • OMAPL138 ARM Reference GEL File.
  • OMAP-L1x Debug GEL File: This can be used with CCS to print out useful debug information such as silicon revision, bootloader error messages, current PC and PSC states, and more.

• See the below information on using the debugging Tools to debug the processor
  • How to connect to the OMAP-L138/C6748/AM1808 EVM board using CCS
  • OMAP-L138/C6748/AM1808 JTAG

• Below is a collection of information on using the TI provided Booting Tools for the processor
  • Serial UART Boot and Flash Loading Utility for OMAP-L138/C6748/AM1808
    • You need to change the code to according to your own board configure(DDR2 and flash driver) and recompile the executable program.
  • CCS flash writer can be found in the PSP release (eg. DaVinci-PSP-SDK-03.20.00.14\src\utils\)
    • Contains flash writers for NOR/NAND/SPI-FLASH/MMCSD. These writers can be run from withing CCS to write programs to flash for boot.
  • Note: The default flash storage is SPI flash on eXperimenter board and NOR/NAND flash are all on the UI board.

• Below is a link to the processor BSDL Files for verifying PCB connectivity
  • OMAP-L138 BSDL Files.
  • C6748 BSDL Models.
  • AM1808 BSDL Models.

Hardware Debugging Tips

• OMAP-L138/C6748/AM1808 Hardware Debugging Guide

DDR2/mDDR

Most issues with DDR2/mDDR come from incorrect software settings. Double check your settings with the DDR timing spreadsheet:

• DDR timing spreadsheet.

The processor and DDR drive strength configurations can also be the cause of issues. See the following wiki for more information on this topic:

• DDR Interface Drive Strength

Once the software settings are confirmed, the layout itself may be at fault:

• Double check your layout against the routing rules in the processor datasheet
  • The most common layout problem that affects DDR functionality is incorrect stackup. Verify that each DDR routing layer has an adjacent solid ground plane underneath with no cuts.
  • See the following checklist for other issues that can affect functionality:
    • DDR Routing Checklist
• Use maximum values for the timing parameters to increase timing margins
• Slow down the DDR clock to determine if it is limited to a high speed issue