DDR Interface Drive Strength

Introducton

There are two separate methods for controlling the drive strength and output impedance of the TI SoCs and DDR memories. VTP calibration controls the output impedance of the TI SoC DDR pins, while the DDR_DRIVE bits of the DDR controller set the drive strength of the DDR memory.

Drive strength control is only available on the DDR interface. Other pins do not have the ability to modify the drive strength.

VTP Calibration

VTP calibration adjusts the output impedance of the DDR pins for process for voltage, temperature, and process variation. The figure below shows internally how this is done on OMAP-L138. An external resistor is placed on the DDR_ZN pin and tied to ground. The internal calibration transistors p[1:n] are sequentially turned on until the voltage level matches that of the external pin. The value of p[1:n] is then used as the drive strength for all DDR bus pin.

VTP.jpg

Note that the actual value for the p[1:n] vector is only used internally and cannot be set or viewed through software.

Additionally, it is not necessary to precisely match the DDR_ZN resistor with the actual board impedance. Using a standard 49.9 Ohm resistor is recommended.

After a device power up or reset, the VTP initialization sequence found in the user guide must be followed. Although the controller has the option of dynamic calibration, in which VTP calibration occurs constantly in the background, it is recommended to disable dynamic calibration and power down the VTP controller to save power. Temperature variations during run-time will not be significant enough to affect the calibrated value, so only the initial calibration is needed.

DDR Drive Strength Settings

JEDEC compliant DDR2 and mDDR memories also have drive strength control. The TI SoC memory controller has the ability to configure the memory drive strength by setting the DDRDRIVE0/1 bits in the SDCR register. Modifying these values will send out initialization cycles to the memory to modify its drive strength.

For DDR2, memory can be set to normal or weak drive strength. When terminators are used on the data bus, the memory should use normal drive strength. When no terminators are used, the memory should use weak drive strength.

For mDDR, memory can be set to full, 1/8, 1/2, or 1/4 drive strength. When terminators are used on the data bus, the memory should use full drive strength. When no terminators are used, the memory should use 1/2 drive strength.

The above recommendations are only valid for designs following the datasheet routing rules for the DDR2/mDDR interface.

For designs without terminators on the bus, higher drive strengths may be used given that the JEDEC overshoot requirements are still met. Overshoot that is above the specification may result in reliability issues over time.

Summary

To summarize the different drive strength control options:

• VTP Calibration: Controls TI SoC DDR2/mDDR output drive strength
• DDRDRIVE0/1 Bits: Control DDR2/mDDR buffer drive strength