DM814x Overview

PRELIMINARY -- WORK IN PROGRESS

Landing page for DM814x Product Families

Availability Disclaimer

DM814x products are intended for high-volume OEMs and ODMs developing video security, video conferencing, video phones and thin/zero client applications. For other customers, design support is available for DM814x-based products through authorized TI third parties, listed here. For additional information on our video security solutions, please visit our IP network cameraand DVR/NVRpages.

Important Documentation

• DM8148 Datasheet
• DM814x Technical Reference Manual
• DM814x Silicon Errata

Block Diagrams

 

Product Matrix

For a general overview of TI's ARM portfolio, see the ARM Platform Technical Guide Brochure.

Also take a look at the DSP & ARM MPU Selection Tool for help choosing a processor.

Schematics & PCB support; Symbols, Footprints, and Simulation Models

• General hardware design: BGA PCB design
• General Schematic Guidelines
• Schematic Guidelines AM387x schematic check list
• AM37xx schematic check list
• Customer Schematic checklist
• USB layout guidelines
• BGA PCB design guidelines
• BGA power supply decoupling
• SATA guidelines File:DM87xx Sata SpecificationKC.zip
• SATA DM814x TRM File:SATA DM8xx1.pdf
• Ball map in Excel format for DM814x, AM387x File:Centaurus Datasheet Ballmap Final.zip
• OrCad schematic symbol for DM814x, AM387x File:CENTAURUS PRELIM SYMBOL.zip
• Pinmux Utility download and instructions located on the PinMux Utility Wiki.
• GEL Files
• PCB footprints
  • TBD

• BSDL
  • Final version is in device product folder

• IBIS Models
  • Final version is in device product folder

Thermal Use Cases

Refer to appendix C of FCBGA Packaging application note (TBD) for thermal modeling results.

SW Overview

DSP Software & Tools Overview

Code Composer Studio

• CCSv5

SysLink UserGuide

• SysLink UserGuide

HDVPSS UserGuide

• TI81XX_VPSS_Video_Driver_User_Guide

Linux

• PSP releases

Android

• CODEC docs and download
• Rowboat is a community portal for Android on TI ARM® Cortex™-A8 platforms
  • A completely free, open-source project for all customers, developers, and third parties
  • Supported by TI Development team
  • Android base port and graphics support available for TI EVMs and Community boards on rowboat.
  • Includes: Code (binary and source), WiKi, How-to’s, links, IRC, FAQs, and more
• TI Android Development Kit
  • Derived from rowboat to aid customer development and out of the box experience.
  • Stable periodic snapshots (approx. every 6 months) available on www.ti.com
  • Tested by TI quality assurance team
  • Includes product specific documentation
• Commercial support for Android developers is available from Mentor Graphics

FAQs and Other SW Reference Information

• EZSDK download
• EZSDK FAQ
• PSP/Linux FAQ
• Linux Topics
• How to Build a Ubuntu Linux host under VMware
• How to Build a Ubuntu Linux host under VirtualBox
• Instructions for building Qt - A cross-platform application and user interface (UI) framework.

Peripheral Overview

Microprocessor Unit (MPU) Subsystem

The MPU subsystem integrates the following modules
ARM subchip

• ARM® Cortex™-A8 core
  
  • ARM Version 7™ ISA: Standard ARM instruction set + Thumb®-2, Jazelle® RCT Java accelerator,
    and media extensions
    
  • NEON™ SIMD coprocessor (VFP lite + media streaming instructions)
    
• Cache memories
  
  • Level 1: 32KB instruction and 32KB data
    
  • Level 2: 512KB L2 cache.
    
• Interrupt controller with synchronous interrupt lines
  
• Asynchronous interface with core logic
  
• Debug, trace, and emulation features: ICE-Crusher, ETM, ETB modules.

For additional details on CortexA8 click here

C674x DSP Subsystem

• The DSP Subsystem integrates the following modules:
  • C674x DSP CPU
  • 32KB L1 Program (L1P)/Cache (up to 32KB) with Error Detection Code (EDC)
  • 32KB L1 Data (L1D)/Cache (up to 32KB)
  • 256KB L2 Unified Mapped RAM/Cache with Error Correction Code (ECC)

• TMS320C674x DSP CPU and Instruction Set User's Guide
• TMS320C674x DSP Megamodule Reference Guide

High Definition Video Image Co-Processors

• Up to two programmable High Definition Video Image Co-Processing Engines (HDVICP2 or also referred to as IVA-HD)
• Supports a range of Encode, Decode, and Transcode Operations
• Supports main video codec standards in HW; initial codecs supported in SW are H.264 encode/decode

Memory Management Units (MMU)

The device contains these memory management units (MMU):

• Host ARM subsystem Cortex A8 MMU
• HDVPSS Controller MMU
• DSP/EDMA Shared System MMU (DEMMU) -- DM814x only
• Dynamic Memory Manager (DMM)

Enhanced DMA controller (EDMA)

On-chip Enhanced DMA controller (EDMA) supports 4 simultaneous physical channels and up to 64 programmable logical channels

Interrupt Controller (INTC)

The device has one interrupt controller (INTC) module.

General-Purpose Memory Controller (GPMC)

• 8-/16-bit Wide Multiplexed Address/Data Bus
• 512M-Byte Total Address Space Divided Among up to 8 Chip Selects
• Glueless Interface to NOR Flash, NAND Flash (With BCH and Hamming Error Code Detection), SRAM and Pseudo-SRAM
• Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, etc.)
• Error Locator Module (ELM) Outside of GPMC to Provide Upto 16-Bit/512-Bytes Hardware ECC for NAND

SDRAM

• DDR SW Leveling process TI814x-DDR3-Init-U-Boot

• Dual 32-bit LPDDR/DDR2/DDR3 SDRAM Interfaces:
  • Supports up to LPDDR-400, DDR2-667, and DDR3-667
  • Up to Eight x 8 Devices Total 2 GB Total Address Space
  • Dynamic Memory Manager (DMM):
    • Programmable Multi-Zone Memory Mapping and Interleaving
    • Enables Efficient 2D Block Accesses
    • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
    • Optimizes Interlaced Accesses

On-Chip Memory Controller (OCMC) Subsystem

128K-Byte of general purpose OCMC (On-chip memory controller) RAM

SGX530™ Graphics Accelerator - Only in DM8148

The SGX530™ Graphics Accelerator subsystem accelerates 3-dimensional (3D) graphics applications. The SGX subsystem is based on the core from Imagination Technologies.

HD Video Processing Subsystem (HDVPSS)

Provides high quality display processing, digital video inputs and outputs, HDMI 1.3 transmit, and simultaneous HD/SD analog output with OSD. Refer to the device datasheet and TRM for more details on HDVPSS features.

HDVICP2

• HDVICP2 Codec http://software-dl.ti.com/dsps/dsps_public_sw/codecs/HDVICP2/index_FDS.html

Timers

The device includes several types of timers used by the system software, including 8 general-purpose timers (GP timers) and one watchdog timers (WDT).

UART/IrDA/CIR Overview

The processor contains six Configurable UART/IrDA/CIR Modules

Inter-Integrated Circuit (I2C) Module

The device contains four Inter-Integrated Circuit (I2C Bus™) Ports.

McSPI

The multichannel serial port interface (McSPI) is a master/slave synchronous serial bus. There is four Serial Peripheral Interfaces (SPIs) [up to 48-MHz]

McBSP

The multi-channel buffered serial port (McBSP) provides a full-duplex direct serial interface between the device and other devices in a system such as other application chips (digital base band), audio and voice codec (AIC23 device), etc. Because of its high level of versatility, it can accommodate to a wide range of peripherals and clocked frame oriented protocols.

The device provides one instance of the McBSP module.

McASP

The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and similar formats

Secure Digital/Secure Digital I/O (SD/SDIO) Card Interface

The processor contains three MMC/SD/SDIO Serial Interfaces [up to 48-MHz]

Universal Serial Bus (USB)

The device includes two USB ports with integrated 2.0 PHY.

• Supports USB 2.0 peripheral at speeds HS (480 Mb/s) and FS (12 Mb/s)
• Supports USB 2.0 Host at speeds HS (480 Mb/s), FS (12 Mb/s), and LS (1.5 Mb/s)
• Supports End Points 0-15

General Purpose I/O (GPIO) Interface

The general-purpose interface combines six general-purpose input/output (GPIO) banks.

The device contains four GPIO modules and each GPIO module is made up of 32 identical channels.

These pins can be configured for the following applications:

• Data input (capture)/output (drive)
• Keyboard interface with a debounce cell
• Synchronous interrupt generation (in active mode) upon the detection of external events (signal

transition(s) and/or signal level(s)).

Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Module

The EMAC controls the flow of packet data from the system to the PHY. The MDIO module controls PHY configuration and status monitoring.

Both the EMAC and the MDIO modules interface to the system core through a custom interface that allows efficient data transmission and reception. This custom interface is referred to as the EMAC subsystem module and is considered integral to the EMAC/MDIO peripheral.

The EMAC module is used to move data between the device and another host connected to the same network, in compliance with the Ethernet protocol.

PCIe

• The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. The device implements a single one-lane PCIe 2.0 (5.0 GT/s) Endpoint/Root Complex port.

SATA

• Serial ATA (SATA) 3.0 Gbps Controller With Integrated PHY
  • Direct Interface to One Hard Disk Drive
  • Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
  • Supports Port Multiplier and Command-Based Switching

SmartReflex™

• Supports SmartReflex™ Technology (Level 2)
  • Based on the device process, temperature, and desired performance, the SmartReflex™ module advises the host processor to raise or lower the core 1-V supply voltage for minimal power consumption. The communication link between the host processor and the external power regulator can be accomplished using GPIOs or I2C.

Development and Reference Designs

Reference Designs

• Z3-DM8148-MOD is a compact OEM-ready module from Z3 Technology based on the DM8148.

Tools

• PSP_Flashing_Tools is a flashing tool for NAND, NOR, and SPI on the DM8148.

Related End Equipments

The links at the TI website below provide block diagrams, application notes, tools, software, design considerations, and other related information for various Video and Imaging end-equipment products.

• End-Equipment Solutions

Training Material

• High-level overview videos are available today in the product folders.

FAQ's

• What are some advantages of these device families?
  • Pin for Pin compatible set of devices for design flexibility
    • The DM814x device families are all pin for pin compatible
  • Up to 50% reduction in system cost due to high integration
    • Memory Controller support DDR2/DDR3 providing flexibility to choose memory
    • Integrated USB PHYs, SATA PHYs, PCIe PHY, HDMI TX PHY.

• How can I determine which product in the DM814x families is the best choice?
  • Target Applications:
    • DM814x: Video Security, Video Conferencing, Video Infrastructure, Media Server, Digital Signage
  • Please refer to the Product Matrix to see the different features supported by each device.

• What are key care abouts for board design?
  • Please refer to the routing, design and layout specifications in the following sections of the datasheet: DDR, SATA, PCIe, USB, HDMI, and Video DAC.

• How can I determine if these devices would be able to meet my feature needs with the existing pin mux?
  • Please refer to the PinMux Utility Wiki.

• How can I conntect JTAG to the device?
  • Please refer to CCS JTAG Connection.

Useful Links

• DSP & ARM MPU Selection Tool

• DaVinci Product line

• E2E Forums - Visit these sites to ask questions and search for answers

Internal Forums:

• DM816x

• DM814x

External Forums:

• DM816x

• DM814x

For access to pre-release documents, please contact Tom Ballew at ballew@ti.com.