TI814x-DDR3-Init-U-Boot

TI814x-DDR3-Init-U-Boot

ReadMe First

The purpose of this document is to describe the approach to fine tune the DDR PHY on TI814x devices with SW leveling.SW leveling can be done in two methods

• Byte wise SW leveling (For 32 bit DDR interface only)

Data macro for each byte lane is leveled independently. The Slave ratio search program will calculate optimal values for each byte lane.

• Word wise SW leveling (For 32 bit or 16 bit DDR interface)

The Slave ratio search program will calculate common optimal value that works for all four byte lanes.

Recommendation: It is advised to perform byte wise leveling to compensate for the trace length delays for each byte lanes accurately, especially at higher frequencies of operation as compared to the word wise leveling.

This wiki page talks about Byte wise SW leveling.For word wise SW leveling follow the link http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot_Wordwise_SWleveling

Prerequisites

1. Excel spreadsheet for obtaining the seed values which is the input to the CCS based app File:RatioSeed TI814x.zip
2. CCS based program DDR3_SlaveRatio_ByteWiseSearch_TI814x.out File:DDR3 SlaveRatio ByteWiseSearch TI814x.zip
3. TI814x U-Boot source code based on PSP release 04.04.00.02
4. TI814X GEL File File:TI814x ddr3.zip
5. U-Boot User Guide which is a part of the PSP release
6. CCS 5.1 or above installed on Windows XP with Service Pack 2
7. Details of CCS 5.1 installation guidelines are given in http://processors.wiki.ti.com/index.php/Category:Code_Composer_Studio_v5

Download all the required file to the PC before proceeding to the next step.

Overview

In order to correctly setup DDR PHY in TI814x devices the approach used is Byte wise software leveling(To find the optimum DDR PHY slave ratio values for each byte lane).The DDR PHY has to be fine tuned based on the PCB trace lengths in order to compensate for the signal propagation delays accurately.

Important Note: SW leveling process is not intended to diagnose a non-working DDR interface. It is only intended for fine tuning the DDR PHY when the DDR interface is functionally working.

The leveling process involves the following steps

1. Obtaining accurate PCB trace lengths (in inches) for the DDR CK trace and DQS trace (Data signal).
2. Calculate the seed values to be input to the slave ratio search program ie:“DDR3_SlaveRatio_ByteWiseSearch_TI814x.out” as described in the subsequent sections.
3. Configure the DDR controller (Also referred as EMIF) with the timing parameters calculated from the spreadsheet File:DM814x DDR Controller Register Configuration spreadsheet v1.0.zip based on the timing parameters mentioned in the data sheet of the specific DDR device being used.
4. Configure the DDR PHY slave ratio registers with the respective seed values calculated from the spreadsheet.

Important Note: DDR memory access is expected to be working upon completion of the above mentioned steps. If not, choose a lower frequency of operation and repeat steps 1 to 4 until the basic memory access is working. It is meaningless to proceed further with SW leveling if the memory access is not working. Remaining steps will only help in getting the optimum DDR PHY slave ratio parameters.

5.Running the CCS based slave ratio search program on the device and collecting the optimum slave ratio values for the specific frequency of operation.

6.Programming the optimum values to the DDR PHY registers replacing the seed values that were programmed initially.

7.To read back the programmed DDR controller and DDR PHY configurations,Load the gel file File:DM814x DDR Config ReadBack.zip ,Run the hotmenu "DDR0_RegisterReadBack" for DDR0 and Run the hotmenu "DDR1_RegisterReadBack" for DDR1.

The slave ratio search program searches for the working range of the following Slave Ratio values based on the initial seed values keyed in on the command line,as explained in the next section.

1. Read DQS Slave Ratio
2. Read DQS Gate Slave Ratio
3. Write DQS Slave Ratio
4. Write DATA Slave Ratio

Please note that the DDR PHY has to be fine tuned each time when there is a change in the PCB layout(ie.when a new revision of the HW is made) or when the frequency of operation changes.

Obtaining the seed values

The seed values for the ratios may be obtained using the File:RatioSeed TI814x.zip spreadsheet. The spreadsheet takes the following as inputs:

1. DDR3 clock frequency
2. CK and DQS trace lengths in inches for each of the byte lanes.

The user inputs should be entered on those cells that are marked green. Then spreadsheet will generate respective seed values at B17, B18 and B19 .These parameters should be passed to the CCS based slave ratio search program.

Running the CCS based slave ratio search program on the target hardware platform

Hardware and CCS Setup

NOTE

You can skip this step if CCS is already configured. Make sure the settings are as mentioned in the configure step.

• Connect the JTAG emulator to the TI814x using the JTAG ribbon cable and the 20/14 pin JTAG adapter (board specific).
• Make sure the Boot Mode / Configuration Select Switch are set to all 0s.
• Start CCSv5.1 by navigating to 'Start' menu in Windows XP
• Select the workspace folder where you want to store your project
• Use target configuration file ti814x.ccxml. If there is a need to crate a new configuration, then follow steps below
  • Select new Target Configuration "View -> Target Configurations",Right click on "User Defined" folder then New Target Configurations
  • Connection = TI XDS560 Emulator
  • Board or Device = TI814xEVM (On some CCS versions you might have to use the internal name of TI814x or Centaurus for this)
  • Save configuration, e.g., ti814x.ccxml
  • From next run, the project and target configuration will be readily available and can be skipped
• Select "Debug Perspective" in CCS if it is not there already: Window -> Open Perspective -> Debug
• Select View -> Target Configurations. Look for the target configuration ti814x.ccxml created in the previous step
• Right click and click "Launch Selected Configuration" this should launch debug session
• In Debug view select "TI XDS560 Emulator_0/Cortex A8" connection.
• Right click and select "Set Debug Scope" option. This will make remove all the cores except Cortex A8 from the debug view.
• Right click on the Cortex A8 core listed and click on "Connect Target"
• A "Disassembly" view with PC halted should pop up in one of the tabs. If not, issue a 'System Reset' from Run menu and then click on Halt

Note: The steps mentioned above holds well for TI XDS560 Jtag emulator. User is advised to follow appropriate steps if a different emulator is being used

Generating the static values

Loading GEL File

• Ensure that the GEL file File:TI814x ddr3.zip is copied to the Windows Machine
• Select Tools -> GEL Files in CCS
• This opens a new tab in the Debug view. On right hand side empty area in this window, right click and use "Load GEL"
• Navigate to the directory containing gel file and select TI814x_ddr3.gel
• A "Scripts" menu item (on top) should now be available
• Select Script -> TI814x DDR Configuration -> DDR3_EMIF0_EMIF1_400MHz_Config
  
• This will perform DDR3 initialization.
• On success, you should see following at the CCS console:

CortxA8: GEL Output: 	 ****  Configuring DDR PLL to 400 MHz.........
CortxA8: GEL Output: 	DM814x DDR DPLL CLKOUT  value is  = 400
CortxA8: GEL Output: 	DM814x DDR3 EVM EMIF0 and EMIF1 configuration in progress.........
CortxA8: GEL Output: 	DM814x DDR,DMM PRCM configuration is Done
CortxA8: GEL Output: 	DM814x DDR PHY Configuration is Done
CortxA8: GEL Output: 	DM814x DDR IO Control Configuration is Done
CortxA8: GEL Output: 	DM814x VTP Configuration is Done
CortxA8: GEL Output: 	DM814x DMM LISA register Configuration is Done
CortxA8: GEL Output: 	DM814x DDR3 EVM EMIF0 and EMIF1 configuration is DONE. . 

• Note that sometimes the Scripts menu is disabled. In this case, go to Debug window and select "TI XDS560 Emulator_0/CortexA8 (top level node) and the Scripts menu should get activated.

Loading the Slave Ratio Search Program

• At this point, A8 in in user(USR) mode (marked as USR in the bottom right corner of CCS Status Bar). It needs to be in Supervisor(SPV) mode to run U-Boot and the Linux Kernel. Follow these steps:

1. Goto menu View -> Registers
2. Expand CPSR
3. Select “M” and set it to 0x13
4. These steps set the CPSR.M to 0x13 (SPV mode).
5. Goto Tools -> ARM Advanced Features select NEON Enabled

• Select Run -> Load -> Load Program. Select the CCS program DDR3_SlaveRatio_ByteWiseSearch_TI814x.out for loading.

Running the Slave Ratio Search Program

Run:

Enter 0 for DDR Controller 0 & 1 for DDR Controller 1
0

DDR START ADDR=0x80000000

Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window
0xA5

Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window
0x34

Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
0x13

Enter the input file Name
Ti814x_Ratio_values

*********************************************************
Byte level Slave Ratio Search Program Values
*********************************************************
                      BYTE3   BYTE2  BYTE1   BYTE0
*********************************************************
Read DQS MAX           5d      60      5f      69
Read DQS MIN            8       8       4       8
Read DQS OPT           32      34      31      38
*********************************************************
Read DQS GATE MAX     1ec     1d1     1b5     1a0
Read DQS GATE MIN      8f      7c      63      41
Read DQS GATE OPT     13d     126     10c      f0
*********************************************************
Write DQS MAX          97      a3      8c      8b
Write DQS MIN           0       0       0       0
Write DQS OPT          4b      51      46      45
*********************************************************
Write DATA MAX         b0      af      b5      b0
Write DATA MIN         4d      52      55      5b
Write DATA OPT         7e      80      85      85
*********************************************************
===== END OF TEST =====  

Note : In the above example the output result gets saved in "Ti814x_Ratio_values.txt" file.

Note:

1. SW leveling has to be performed on each EMIF separately and each PHY configured accordingly if the trace lengths are significantly different for each EMIF.
2. The slave ratio program expects EMIF0 to be configured for a base address of 0x8000:0000 and EMIF1 to be at oxC000:0000. The DMM LISA registers has to be configured accordingly as shown in the File:TI814x ddr3.zip gel file. Please note that user can choose a different base address for the DDR memory space (if needed) post the SW leveling.

The optimum slave ratio values may vary by small margin, if the SW leveling is performed multiple times. This is due to possible change in the environment variables such as Core/IO voltages and temperature.

Reset the Board or Issue POR. Repeat the steps for searching for the slave ratios for different DDR2/3 frequencies.

Modifying U-Boot

The values generated in the previous step are used in U-Boot for the byte-wise software leveling process. While plugging in the values in U-Boot please ensure that the changes are done for the same clock speed for which the program was executed in the previous step.

• Open the file arch/arm/include/asm/arch-ti81xx/ddr_defs_ti814x.h

The values obtained in the previous step need to be plugged under the TI814X appropriate #define in the order emif0 : emif 1. There are seperate macro for each byte lane suffixed with BYTE<n>

/* TI814X DDR3 PHY CFG parameters   <emif0 : emif 1> */
#define DDR3_PHY_RD_DQS_CS0_BYTE0              ((emif == 0) ? 0x38 : 0x3A)
#define DDR3_PHY_RD_DQS_CS0_BYTE1              ((emif == 0) ? 0x37 : 0x36)
#define DDR3_PHY_RD_DQS_CS0_BYTE2              ((emif == 0) ? 0x32 : 0x37)
#define DDR3_PHY_RD_DQS_CS0_BYTE3              ((emif == 0) ? 0x31 : 0x33)

#define DDR3_PHY_WR_DQS_CS0_BYTE0              ((emif == 0) ? 0x43 : 0x49)
#define DDR3_PHY_WR_DQS_CS0_BYTE1              ((emif == 0) ? 0x44 : 0x4E)
#define DDR3_PHY_WR_DQS_CS0_BYTE2              ((emif == 0) ? 0x53 : 0x54)
#define DDR3_PHY_WR_DQS_CS0_BYTE3              ((emif == 0) ? 0x50 : 0x50)

#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE0         ((emif == 0) ? 0xE4 : 0xD3)
#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE1         ((emif == 0) ? 0x111 : 0xF7)
#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE2         ((emif == 0) ? 0x112 : 0x109)
#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE3         ((emif == 0) ? 0x13D : 0x135)

#define DDR3_PHY_WR_DATA_CS0_BYTE0             ((emif == 0) ? 0x85 : 0x8A)
#define DDR3_PHY_WR_DATA_CS0_BYTE1             ((emif == 0) ? 0x83 : 0x80)
#define DDR3_PHY_WR_DATA_CS0_BYTE2             ((emif == 0) ? 0x85 : 0x7F)
#define DDR3_PHY_WR_DATA_CS0_BYTE3             ((emif == 0) ? 0x7F : 0x85)

Note: All the above values are generated by running the byte-wise leveling app on TI814X EVM and this might vary for each board.

Register to U-Boot Macro Definition Mapping Table

Register Name	Constant Name	File
SDRCR	DDR3_EMIF_SDRAM_CONFIG	DDR_DEFS_TI814x.h
SDRRCR	DDR3_EMIF_REF_CTRL	DDR_DEFS_TI814x.h
SDRRCR2	Not Used	N/A
SDRTIM1	DDR3_EMIF_TIM1	DDR_DEFS_TI814x.h
SDRTIM2	DDR3_EMIF_TIM2	DDR_DEFS_TI814x.h
SDRTIM3	DDR3_EMIF_TIM3	DDR_DEFS_TI814x.h
PMCR	Not Used	N/A
PBBPR	Not Used	N/A
ZQCR	DDR3_EMIF_SDRAM_ZQCR	DDR_DEFS_TI814x.h
DDR_PHY_CR	EMIF4_0/1_DDR_PHY_CTRL_1	DDR_DEFS_TI814x.h
PRI_COS_MAP	Not Used	N/A
CONNID_COS_1_MAP	Not Used	N/A
CONNID_COS_2_MAP	Not Used	N/A
RD_WR_EXEC_THRSH	Not Used	N/A
DDRIOCTRL	DDR0/1_IO_CTRL	DDR_DEFS_TI814x.h

• Rebuild and flash U-Boot as described in the U-Boot user guide.

FAQ

Q. How to enable single EMIF configurations on TI8148 u-boot ?

Ans: To enable single EMIFconfiguration we have to apply the patch file File:Ti8148 single emif patch.zip and change the values of the macro USE_EMIF1 to 0 in the "arch/arm/include/asm/arch-ti81xx/ddr_defs_ti814x.h"

This patch disables the configurations for the 2nd EMIF instance in the evm file and also it uses a minimal non-interleaved LISA_MAP configurations.