DM8127 DDR Config Resources

DM8127 DDR Config Resources

Introduction

The DM8127, is a member of the DM814x family of System on Chip devices. The DM8127 has (2) DDR2/3 interfaces, each is capable of 1Gbyte addressing. Having 2 DDR interfaces with different board layout parameters, means that you have to be more careful in the testing and programming portions AND you have two sets of DQS and Clock invert calculations, and programmation registers to update.

The operating mode OPP of the DM8127 is listed in the datasheet Table 8-4. This determines the DDR clock for the Controller configuration.

OPP #	DDR Clock rate
100	400Mhz
120	400Mhz
166	533Mhz

The DDR Controller, is discussed in the DM814x Technical Reference Manual. There are (2) DDR PHY implementations, to allow for different layout corrections for DFE clock polarity, and layout skew delays.

The memory-size of the DDR3, is normally dependent on the device application. In this example we have (2 sets) of 2 x16 DDR3, 256M x 32bits, 4Gbit devices. Each DDR set provides 1Gbyte total DDR memory.

DM8127 EVM DDR3 (2sections) interface

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DM38x Specific Instructions

The DM813x, DM814x DDR Configuration spreadsheet is used for programmation. [1]
An example of this spreadsheet is attached, based on the DM8127 EVM configuration (note currently the same as the DM388 EVM configuration) - File:DM813x DDR Controller DM388.xlsx.zip

There are several key parameters needed for the DDR controller programmation:
Under the DDR Controller Register tab..

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F3 - Enter the DDR type
F4 - Enter the DDR clock rate (based on OPP mode) (single edge rate)
Additional - Entries in white highlighted boxes mostly rows 12 - 22.

Under the DDR DRAM tab ..

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Enter the DDR device datasheet parameters from F10 - G34
Based on the spreadsheet calculations, you copy the DDR controller registers hex values on the DDR Controller Registers tab I3 - R9

Using the device datasheet, you would obtain the DDR Controller memory offset address, and Using the DM38x Technical Reference Manual add the DDR Controller device offset addresses, and program the C programming file.

Since the DM8127 has two DDR3 PHYs with two different layouts of DDR3 SDRAMs, there are two sets of calculations for the DQS and clock invert calculations. The DDR3 Controller must have search parameters for the proper DQS strobes for DDR3 memory. After following the DDR3 layout guidance in the datasheet and Technical Reference manual, the word-wise, or byte-wise(preferred) DQS seed value is calculated in the spreadsheet, found in the DM814x DDR Software Leveling wiki. [2] The calculations from the spreadsheet are used with CCS and GEL to test the DDR, DQS and clock invert values.

Here is an example of the entries from the layout file, used with the DSP program and GEL file to check the DDR on your board. Note: there are two sets of calculations. The DDR clock output is inverted if the shortest data path trace is shorter than the DDR clock trace.

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Note: you enter the seed values at the bottom of the graphic into the GEL file, when you test your DDR3 subsystem on your board. The GEL file searches for the DQS parameters that work with the specific layout of your board. In the next graphic, is the GEL file output for the DM8127 EVM, again there are two sets of calculated values needed.

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Note: remember to test several boards, and if needed voltage margining, and temperature cycling to insure the DQS final values work for your design.

References:
DM8127 datasheet - [3],
DM8127 Hardware Design Guide - [4],
DM8127, DM814x Technical Reference Manual – [5]
DM814x DDR Controller Configuration spreadsheet - [6]
DM814x DDR Software Leveling wiki - [7]