DM385 and DM388 DDR Config Resources

Introduction

This page provides the DDR Configuration resources for DM38x devices.

The DDR controller within the TSM320DM38x SOCs can accommodate DDR2 and DDR3 devices. This description discusses the EVM selection of DDR3,

selection of system parameters, and the programmation of the DDR registers. The operating mode OPP of the DM385/388 is listed in the datasheet Table 7-3. This determines the DDR clock for the Controller configuration.

OPP #	DDR Clock rate
100	400Mhz
120	400Mhz
Turbo	533Mhz
Nitro	533Mhz

1, 2, and 4 DDR3 devices can be implemented in a single rank topology. The DDR databus is 16 or 32bits wide. The memory-size of the DDR3, is normally dependent on the device application. In this example we have (2) x16 DDR3, 4Gbit devices. They provide 1Gbyte total DDR memory, 256Mx32bits.

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DM38x Specific Instructions

The DM813x, DM814x DDR Configuration spreadsheet is used for programmation. [1]
An example of this spreadsheet is attached, based on the DM388 EVM configuration - File:DM813x DDR Controller DM388.xlsx.zip

There are several key parameters needed for the DDR controller programmation:
Under the DDR Controller Register tab..

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F3 - Enter the DDR type
F4 - Enter the DDR clock rate (depending on OPP mode) (single edge rate)
Additional - Entries in white highlighted boxes mostly rows 12 - 22.

Under the DDR DRAM tab ..

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Enter the DDR device datasheet parameters from F10 - G34
Based on the spreadsheet calculations, you copy the DDR controller registers hex values on the DDR Controller Registers tab I3 - R9

Using the device datasheet, you would obtain the DDR Controller memory offset address, and Using the DM38x Technical Reference Manual add the DDR Controller device offset addresses, and program the C programming file.

The DDR3 Controller must have search parameters for the proper DQS strobes for DDR3 memory. After following the DDR3 layout guidance in the datasheet and Technical Reference manual, the word-wise, or byte-wise(preferred) DQS seed value is calculated in the spreadsheet, found in the DM814x DDR Software Leveling wiki. [2] The calculations from the spreadsheet are used with CCS and GEL to test the DDR, DQS and clock invert values.

Here is an example of the entries from the layout file, used with the DSP program and GEL file to check the DDR on your board. In the next graphic you enter the values in green. The DDR clock output is inverted if the shortest data path trace is shorter than the DDR clock trace.

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Note: you enter the seed values at the bottom of the graphic into the GEL file, when you test your DDR3 subsystem on your board. The GEL file searches for the DQS parameters that work with the specific layout of your board. In the next graphic, is the GEL file output for the DM388 EVM. You also need to take the GEL file output, and write these DQS values into the C programmation file for your DDR implementation.

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Note: remember to test several boards, and if needed voltage margining, and temperature cycling to insure the DQS final values work for your design.

References: DM385/DM388 Datasheet - [3]
TMS320DM38x Technical Reference Manual – [4]
DM814x DDR Controller Configuration spreadsheet - [5]
DM814x DDR Software Leveling wiki - [6]