DM36x to DM368 NAND UBL porting guide

About this Guide

This is reference guide to port UBL for DM368 using DM365 UBL code base. This guide helps to configure PLLs to run ARM@432 and DDR@340 with 24MHz crystal oscillator. Modify PLL1, PLL2 and DDR setup function in DM36x/Common/src/device.c as explained in below sections.

PLL1 Setup

Modify DEVICE_PLL1Init(PLL1_Mult) function for 680MHz by replacing configurations of PLL1 multipliers, pre and post divisors as below

<syntaxhighlight lang="c">

   //Program the Multiper and Pre-Divider for PLL1
PLL1->PLLM   =   0x55;   // VCO will 24*2M/N+1
PLL1->PREDIV =   0x8000|0x5;

    // Post divider setting for PLL1

        PLL1->PLLDIV1 = 0x801B;
        PLL1->PLLDIV2 = 0x8001;
        PLL1->PLLDIV3 = 0x8001;   // POST DIV 680/2 = 340Mhz  -> MJCP and HDVICP bus interface clock
        PLL1->PLLDIV4 = 0x8003;   // POST DIV 680/4 = 170Mhz  -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus interface clk)
        PLL1->PLLDIV5 = 0x8001;   // POST DIV 680/2 = 340Mhz  -> VPSS
        PLL1->PLLDIV6 = 0x8008;   // POST DIV 680/9 = 75.6 Mhz -> VENC

        PLL1->PLLDIV7 = 0x8000;   // POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils down to 340 Mhz)
        PLL1->PLLDIV8 = 0x8006;   // POST DIV 680/7= 97Mhz-> MMC0/SD0
        PLL1->PLLDIV9 = 0x801B;   // POST DIV 680/28 = 24.3Mhz-> CLKOUT

</syntaxhighlight>

PLL2 Setup

Modify DEVICE_PLL2Init()function for 432MHz by replacing configurations PLL2 multipliers, pre and post divisor as below

<syntaxhighlight lang="c">

 //Program the Multiper and Pre-Divider for PLL2
    PLL2->PLLM   =   0x9;   // VCO will 24*2M/N+1 = 432Mhz
    PLL2->PREDIV =   0x8000|0x0;

 // Post divider setting for PLL2
    PLL2->PLLDIV1 = 0x8011;
    PLL2->PLLDIV2 = 0x8000;   // POST DIV 432/1=432 Mhz  -> ARM926/(HDVICP block) clk
    PLL2->PLLDIV3 = 0x8001;
    PLL2->PLLDIV4 = 0x8014;   // POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk
    PLL2->PLLDIV5 = 0x800F;   // POST DIV 432/16=27 Mhz  -> VENC(For SD modes, requires )

</syntaxhighlight>

NOTE

1. For configuration details of PLL Controllers (PLL1 and PLL2) look into TMS320DM36x ARM Subsystem Reference Guide (literature number SPRUFG5).
2. Make sure PLLC1_SYSCLK6 is selected for HD modes and is done by configuring VPSS_CLK_CTRL register(i.e. VPSS_CLK_CTRL = 0x18) in drivers/media/video/davinci/davinci_platform.c. VENC requires clock of 74.25Mhz for HD modes to work properly. HD output is tested on TV with above derived clock of 68Mhz.
3. Make sure PLLC2_SYSCLK5 is selected for SD modes and is done by configuring VPSS_CLK_CTRL register(i.e. VPSS_CLK_CTRL = 0x38) in drivers/media/video/davinci/davinci_platform.c. VENC requires clock of 27Mhz for SD modes to work properly.

DDR2 Setup

Modify DEVICE_DDR2Init() for 340MHZ by replacing SDR bank and timing configurations as below <syntaxhighlight lang="c">

  DDR->DDRPHYCR = 0x000000C6;
  DDR->SDBCR = 0x00D34A32;        //Program SDRAM Bank Config Register
  DDR->SDBCR = 0x0053CA32;

  DDR->SDTIMR  =0x576D7D12;       //Program SDRAM Timing Control Register1
  DDR->SDTIMR2 =0x422EC742;       //Program SDRAM Timing Control Register2

  DDR->PBBPR = 0x000000FE;

  DDR->SDBCR = 0x08534832;        //Program SDRAM Bank Config Register

  DDR->SDRCR = 0xA5C;             //Program SDRAM Refresh Control Register

</syntaxhighlight>

NOTE
The timing configuration done above are specific to DDR part present on the evm's. Please refer DDR device data sheet for information.

Build steps

1. Open DM36x/CCS/UBL/UBL.pjt UBL project.
2. Make sure you selected BOOT_NAND configuration from active configuration drop down.
3. Build the project and new binary at DM36x\CCS\UBL\UBL_DM36x_NAND.bin does the PLL configurations to run ARM@432 and DDR@340.