DM/AM37 SDRC registers configure in x-loader

Introduction

The following information describes how to set the SDRC registers in the DM/AM37 SDRC module depending on the mDDR memory that you are using. Both 16-bit and 32-bit mDDR configurations are addressed in this wiki.

CS specific registers

Each of these registers are defined for each chip select (CS0 and CS1). If you are using both chip selects, ensure that you set both register accordingly. If you are using only CS0, CS1 register can be left in their default state.

• SDRC_MCFG_p
  •  a) Refer to the AM/DM37x RTM SDRC Register Manul chapter for SDRC_MCFG_p.
  •  b) Here are some tips to configure each value:
    • LOCKSTATUS - This bit should remain 0 for full use of the MCFG register.
    • RASWIDTH, CASWIDTH - these values depend on the configuration of the memory. In the TRM, go to the table entitled “SDRC Address Multiplexing Scheme Selection vs SDRAM Configurations” (there is a table for 32 bit or 16 bit memory interface). Determine the configuration of your memory (eg. 64M x 32) and total size (eg, 2048Mbits) to conclude how many row and column address bits to set. In this example, 10 column bits and 14 row bits. So RASWIDTH = 0x3, CASWIDTH = 0x5.
    • ADDRMUXLEGACY - should always be set to 1 in order to use RASWIDTH and CASWIDTH as described above.
    • RAMSIZE - total capacity of memory, divided into 2MByte chunks.
      
      • Example: 512MB total / 2MB chunks = 256. RAMSIZE = 0x100
    • BANKALLOCATION - these bits are used to optimze the bandwidth in and out of the mDDR. Section "BANKALLOCATION Parameter" in the TRM describes the details. To optimize your bandwidth, you need to determine which access pattern you typically use in your application, and set the BANKALLOCATION bits accordingly. This can potentially reduce the overhead of accessing the mDDR, resulting in improved performance.
    • B32NOT16 - 16bit or 32bit bus width
    • DEEPPD - does your memory support deep power down? If so, set this to 1
    • DDRTYPE - always set to 0
    • RAMTYPE - for mDDR set to 0x1
  •  c) In the x-loader, macro SDP_SDRC_MDCFG_0_DDR is used to store it.
  •  d) In the x-loader, in function config_3430sdram_ddr(),SDRC_MCFG_p is configured.    
  •  e) For CS0 & CS1 are all enabled, please do it as in c) & d) to add for SDRC_MDCFG_1.
• SDRC_MR_p
  •  a) Refer to the AM/DM37x RTM SDRC Register Manul chapter for SDRC_MR_p.
  •  b) CAS latency can be get from the memory datasheet, and the typical value is 3.
  •  c) The other values are follow RTM’s define.
  •  d) In the x-loader, macro SDP_SDRC_MR_0_DDR is used to store it.
  •  e) In the x-loader, in function config_3430sdram_ddr(),SDRC_MCFG_p is configured.
  •  f) For CS0 & CS1 are all enabled, please do it as in c) & d) to add for SDRC_MR_1.
• SDRC_EMR2_p
  •  a) Refer to the AM/DM37x RTM SDRC Register Manul chapter for SDRC_EMR2_p.
  •  b) The typical value for this case is 0x0000000, so it is not specially configured in x-loader.

AC timing registers

• SDRC_ACTIM_CTRLA_p and SDRC_ACTIM_CTRLB_p
  •  a) Refer to the AM/DM37x RTM SDRC Register Manul chapter for SDRC_ACTIM_CTRLA_p& SDRC_ACTIM_CTRLB _p.
  •  b) Please refer to the tool OMAP35x/AM/DM37x DDR register calc tool.
  •  c) In the x-loader, in function config_3430sdram_ddr(),the SDRC_ACTIM_CTRLA_0 is configured. And You can also add the configured for CS1 related memory as for CS0, which is default.
  •  d) Note: i. The tCK value should represent the speed at which you will be running the device (not necessarily the minimum value in the datasheet). The register values for the OMAP35x/ AM37x AC timing registers will be calculated based on these inputs. For more conservative values, you can back off these optimal values (ie, increase each value by 1 or 2).

Setting Refresh rate

•  SDRC_RFR_CTRL_P
  • a) Refer to the AM/DM37x RTM SDRC Register Manul chapter for SDRC_RFR_CTRL_P.
  • b) tREFI can be get from the memory datasheet, typically in us range; some datasheets may refer to a "Refresh Interval time" in the millisecond range (64ms, for example).
  • c) ARCV = tREFI/tCK – 50, For 200MHz, system, tCK = 5ns.
  • d) Use same value for SDRC_RFR_CTRL_0.ARCV and SDRC_RFR_CTRL_1.ARCV.
  • e) ARE value is typically 0x1 to perform one autorefresh command each time the autorefresh command counts down to 0.
  •  f) In the x-loader, in function config_3430sdram_ddr(),the SDRC_RFR_CTRL_0 is configured. And You can also add the configured for CS1 related memory as for CS0, which is default.

General Registers

• SDRC_SYSCONFIG
  •  a) Refer to the AM/DM37x RTM SDRC Register Manul chapter for SDRC_SYSCONFIG.
  •  b) typical value for normal operation: 0x00000010:
    •  i. NOMEMORYMRS - typically set to 0 to allow commands to be sent to the mDDR
    •  ii. IDLEMODE - set to 0x2 to enable Smart Idle. All other settings are reserved.
    •  iii. SOFTRESET - set to 0 for normal mode.
  •  c) In the x-loader, in function config_3430sdram_ddr(), the SDRC_ SYSCONFIG is configured.
• SDRC_CS_CFG
  •  a) Refer to the AM/DM37x RTM SDRC Register Manul chapter for S SDRC_CS_CFG.
  •  b) This register configures CS1 address space, Typically only CS0 is used, but if your application requires more capacity, or if your memory configuration requires the use of 2 chip selects because of loading restrictions, then CS1 would be used. For configurations which use just CS0, this register can be left in its default setting.
  •  c) In the x-loader, in function config_3430sdram_ddr(), the SDRC_ CS_CFG is configured.
    
• SDRC_SHARING
  •  a) Refer to the AM/DM37x RTM SDRC Register Manul chapter for SDRC_SHARING.
  •  b) For 32-bit configurations, the typical value for this register is 0x00000100. This will define a 32-bit data lane for both CS0 and CS1. This setting will work for either CS0 only or CS0/CS1 configurations.
  •  c) For 16-bit configurations, the typical value for this register is 0x00003700. This will define a 16-bit data lane for both CS0 and CS1. This setting will work for either CS0 only or CS0/CS1 configurations.
  •  d) In the x-loader, in function config_3430sdram_ddr(), the SDRC_SHARING is configured.
• SDRC_ERR_TYPE
  •  a) Refer to the AM/DM37x RTM SDRC Register Manul chapter for SDRC_ ERR_TYPE
  •  b) This register is typically left in its default value.
• SDRC_DLLA_CTRL
  •  a) Refer to the AM/DM37x RTM SDRC Register Manul chapter for SDRC_DLLA_CTRL.
  •  b) Typical value is 0x0000000A.
  •  c) In the x-loader, in function config_3430sdram_ddr(), the SDRC_DLLA_CTRL is configured.
• SDRC_POWER_REG
  •  a) Refer to the AM/DM37x RTM SDRC Register Manul chapter for SDRC_POWER_REG.
  •  b) Typical value is 0x00000081.
  •  c) In the x-loader, in function config_3430sdram_ddr(), the SDRC_POWER_REG is configured.