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Talk:C6747 Watchdog example
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I have run into what appears to be a discrepancy in some reference material. I am trying to enable the internal watchdog on the C6747. According to SPRUFM5C (12/2010), the default time base for the 64-bit Timer plus module is the “Internal Clock”. According to the first sentence of section 2.1.2.1, the “internal clock source to the timer is generated by the PLL controller”.
Our board is driven by an oscillator source at 24 MHz. Using the oscillator, the PLL controller provides a system frequency output of 300 MHz. From observation, it appears the timer counter registers when running in 64-bit WDT are being clocked at 24 MHz. Because of the documentation, I expected this input to the timer to be at 300 MHz.
Can you have someone confirm or deny this finding? Is the timer "internal clock" source the oscillator or the PLL output?
--Mjmanthey 12:04, 4 January 2011 (CST)