Talk:AM35x VCA PCB layout

Comments on AM35x VCA PCB layout

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Kentxu said ...

Thanks for the very useful resource!

Any possibility of continuing the design to show how to connect mDDR/DDR2?

Also, it states that "The finished routing for this example is available on the TI website (in the AM3517 product folder) in Allegro format." Please indicate where as I could not find it.

--Kentxu 20:44, 10 June 2010 (CDT)

Nlc said ...

Great ! I plan to design my own SoM with the AM3505 and this article is really great ! If it's possible to route all ball of the processor on a 4 layers pcb, I hope it will be the same for other BGA components (ddr2, nand flash, etc...) !!

I agree with Kentxu, an article to explain how correctly route the DDR2 memoru would be a good idea, because it seems to not be an easy task.

--Nlc 15:55, 23 January 2011 (CST)

Nlc said ...

I started my design, and I follow theses instructions as a start point for the routing. But if I am not wrong, it seems balls G20 and G21 (VSS) are not connected on the above images !?

So where to put the via to connect these ball to gnd layer ?

--Nlc 04:39, 28 February 2011 (CST)

A0321971 said ...

It is possible to route DDR2 on four layers as well. We have done this with trial routing for several of these Via Channel(TM) designs. It's a little challenging, but the key is to have a plan.

For DDR2, address goes up in between the chips and T's out, data goes point to point to each chip. Have a plan and it will work out.

--A0321971 16:19, 2 March 2011 (CST)

Mcg said ...

Nice routing scheme, but I have concerns about this method being manufacturable in qty. The article mentions using 20 mil vias, but doing so pushes the bga pad to via and trace spacing to below typical norms. I have reduced the via size to 18, and still have only 6 mils between bga pad and via, and 5 mils between vias. Typically, we leave 7 mils between bga pads and other copper features (trace/via) due to soldermask oversize (3 mils) and shift (3 mils) to prevent exposed copper. Has anyone else been able to fab boards using this method without fab/assy issues relating to this technique? So far, only 1 of 4 fab houses we've checked with are comfortable with it. Thanks in advance.

--Mcg 08:38, 16 May 2011 (CDT)

A0321971 said ...

Really? I've checked with many customers and PCB fabs and they all seem fine with 4 mils clearance between BGA pad and via. This is what I designed this for, but with this particular array there is more room than some of the others so 6 may be possible with 18 mil vias. This design has been mass produced (not this exact layout, but other layouts using the same through hole design and routing) many times. Where are you located and what kinds of PCB fabs have you been in contact with? Thanks!

--A0321971 08:07, 27 June 2012 (CDT)