StarterWare HSI2C

HSI2C

Introduction

The I2C component is in compliance with the Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1. The I2C module supports only Fast mode (upto 400 kbps) of operation. AM335X I2C can be configured to multiple master-transmitters and slave-receivers mode and multiple slave-transmitters and master-receivers mode. I2C also could be configured to generate DMA events to the DMA controller for transfer of data.

Programming sequence

Interrupt Mode

• Configuring the I2C in master transmitter/Receiver mode
  • The Pin multiplexing registers need to be configured for enabling the I2C_SDA and I2C_SCL pins.
  • The I2C is placed in local reset state using I2CMasterDisable()
  • The required operating clock is set using I2CMasterInitExpClk()
  • The address of the slave to be addressed is set using I2CMasterSlaveAddrSet()
  • The required I2C interrupts are enabled using I2CMasterIntEnableEx()
  • The mode of operation is set using I2CMasterControl()
    • In case of master transmitter mode of operation, the setting used is I2C_CFG_MST_TX. Optionally STOP mode also can be configured. Only after the required settings the module is brought out of reset.
    • In case of master Receiver mode of operation, the setting used is I2C_CFG_MST_RX. Optionally STOP mode also can be configured. Only after the required settings the module is brought out of reset.
• Before Configuring the I2C configuration and DataCount register make sure that I2C registers are ready for access by polling the Access ready bit of IRQ RAW status register.
• Finally the data transfer is started by commanding a START on the bus using I2CMasterStart()
• STOP condition generation
  • STOP can be configured to be automatically generated at the end of ICCNT number of bytes. In this case the I2C_CFG_STOP needs to be passed to I2CMasterControl() and also the ICCNT should be updated with the required number of bytes using I2CSetDataCount()
  • STOP can also be generated by manually. In this case I2C_CFG_STOP need not be supplied. But I2CMasterControl() can be used to set STOP manually.
  • Various combinations decide the STOP generation. Please refer to the I2C Peripheral User Guide for more details.
• Note: In interrupt handler Receive ready status should be cleared only after reading the received data from the I2C data register.

Similarly Transmit ready status sholud be cleared only after writing to I2C data register.

DMA Mode

• In DMA mode of operation, the data transfer happens via EDMA.
• Enable EDMA clocks.
• EDMA is initialized using EDMA3Init(), the DMA channels are mapped and enabled using EDMA3RequestChannel().
• EDMA PaRAM set (options) for HSI2C transmit and receive are set using EDMA3SetPaRAM().
• EDMA transfer is enabled using EDMA3EnableTransfer().
• I2C DMA event generation for HSI2C transmit and receive is enabled using I2CDMATxEventEnable().
• Configure the I2C in Master Transmitter/Receiver Mode as explained for interrupt mode (above).
• A transmit register empty/recieve byte condition generates a Tx/Rx EDMA event.
• The EDMA completion interrupt occurs after number of bytes configured in the PaRAM set are exhausted.
• The generation of I2C EDMA events is disabled using I2CDMATxEventDisable()
• Two interrupt handlers are registered for EDMA
• The completion interrupt handler EDMA3ComplHandlerIsr() to take action on the completion of transfer. Action usually is to disable the channel on completion of transfer.
• The error interrupt handler EDMA3CCErrHandler() to take action on the error conditions. Action usually is to disable the channel, clear error bits and terminating the transfer.