Smart Home and Energy Gateway Hardware Manual

Smart Home and Energy Gateway Hardware Manual

Smart Grid Solutions

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IMPORTANT

This document only applies to revision B of the Smart Home and Energy Gateway reference design. Technical details specific to previous revisions of the Gateway reference design are not included in this document.

Introduction on the Gateway Reference Design

This document describes the hardware architecture of the Smart Home and Energy Gateway reference design which is based on the Texas Instruments AM3352 Cortex-A8 processor.

Key Features

The Smart Home and Energy Gateway is a reference design for home energy gateway products based on the AM335x ARM Cortex-A8 microprocessor family of devices. The reference design includes multiple RF communication interfaces, including: WiFi, Bluetooth, and ZigBee. All of the board design information is freely available and can be used as the starting point for an AM335x-based home energy gateway product.

Smart Home and Energy Gateway

The Gateway reference design comes with a full variety of board devices.  Key features include:

• An AM3352 Cortex-A8 Microprocessor (MPU) running at 600MHz
• Support for WLAN, Bluetooth, and ZigBee communication
• Expansion header for evaluation of different RF solutions, e.g. NFC
• 2-Gbits of DDR3 SDRAM memory
• 2-Gbits of NAND flash memory, 256-Mbits of SPI flash, and a 32-kBit I2C EEPROM
• 1 10/100 Ethernet interface
• 1 USB Host port
• 2 user LEDs
  

Functional Block Diagram

Gateway Block Diagram

The Gateway reference design consists of one main PCB assembly housing the AM3352 Cortex-A8 processor, DDR3 memory, NAND flash, SPI NOR flash, two RF modules, and other peripherals. The AM3352 processor interfaces to the on-board devices through its integrated device interfaces. The processor's DDR 16-bit bus connects directly to the DDR3 memory, while the GPMC bus is connected to the NAND flash.

The reference design uses two RF modules. The R078 (WL1837) WLAN/BT wireless module from TDK enables Wi-Fi and Bluetooth/BLE technology. The R078 module is based on the WiLink8 chip set from Texas Instruments. For ZigBee functionality the reference design uses the RC2400HP ZigBee-Ready RF transceiver module from Radiocrafts. The RC2400HP module is based on CC2530 ZigBee device from Texas Instruments.

One USB port on the processor is connected to a standard A connector for connection to peripheral devices. The Ethernet port on the processor is connected to a 10/100 Ethernet PHY.

The board includes 2 user LEDs which can be used to provide visual feedback. The user LEDs connect directly to the AM3359 processor I/O pins for ease of use.

The board can be powered through a 5-V DC external supply. On-board switching regulators and power management IC (PMIC) provide the necessary voltage rails to power the processor, memory, and on-board peripherals. The processor is held in reset until all voltage rails are within operating specifications.

Texas Instruments Code Composer Studio can be used to debug code running on the board. Code Composer Studio communicates with the board through using an external JTAG emulator. There is no on-board emulation on the reference design.

Basic Operation 

TI's Linux software development kit (SDK) and RF module drivers can be adapted to run on the Gateway reference design. Detailed information about setting up these software components can be found in the Smart Home and Energy Gateway Software Manual.

Configuration Switch Settings

The reference design has one configuration switch (SW2) which configures the boot mode that will be used when the processor is taken out of reset. Refer to the the Switches section for more information.

Power Supplies

The board is powered from an external +5-V DC power adaptor. The external power supply is connected to the DC power input (J2). Multiple switching regulators and a power management IC convert the 5-V DC into the different voltage rails required by the board components and peripherals (see the Power System Design section for more information).

Power Measurement

Multiple test points are available to allow power measurement of various power rails on the board. A power measurement can be conducted by measuring the voltage across the series resistor located on these test points and applying the formula V = I*R. Refer to the Schematics in the Board Design Information section for more information on the location of the power test points.

Board Features

Processor Clocks

The AM3352 device has two internal clock oscillators. One clock oscillator provides the main clock and the other provides the clock for the real-time clock (RTC) module. Each internal oscillator can be connected to an external crystal circuit (oscillator mode) or external LVCMOS square-wave digital clock source (bypass mode). The oscillators automatically operate in bypass mode when their input is connected to an external LVCMOS square-wave digital clock source.

The OSC1 oscillator provides a 32.768-kHz reference clock to the RTC module and is connected to the RTC_XTALIN and RTC_XTALOUT terminals. This clock source is referred to as the 32K oscillator (CLK_32K_RTC) in the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73). OSC1 is disabled by default after power is applied. This clock input is optional and may not be required if the RTC is configured to receive a clock from the internal 32k RC oscillator (CLK_RC32K) or peripheral PLL (CLK_32KHZ) which receives a reference clock from the OSC0 input.

The OSC0 oscillator provides a 19.2-MHz, 24-MHz, 25-MHz, or 26-MHz reference clock which is used to clock all non-RTC functions and is connected to the XTALIN and XTALOUT terminals. This clock source is referred to as the master oscillator (CLK_M_OSC) in the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73). OSC0 is enabled by default after power is applied.

This reference design enables the two clock inputs on the AM335x device. A 24-MHz crystal is connected to the OSC0 oscillator, while a 32-kHz crystal is connected to the OSC1 oscillator.

Processor Resets

The processor has a global power-on reset signal, PWRONRSTn. Everything on device is reset with assertion of power-on reset. This reset is non-blockable. PWRONRSTn can be driven by external power management devices or power supervisor circuitry. During power-up, when power supplies to the device are ramping up, PWRONRSTn needs to be driven low. When the ramp-up is complete and supplies reach their steady-state values, PWRONRSTn need to be driven high. During normal operation when any of the device power supplies are turned OFF, PWRONRSTn must be driven low.

The processor also has a global warm reset, WARMRSTn. WARMRSTn is a bidirectional warm reset signal. As an input, it is typically used by an external source as a device reset. SYSBOOT pins are not latched with a warm reset. The processor will boot with the SYSBOOT values from the previous cold reset.

Refer to AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (lit number SPRUH73) for a full summary of the differences between a warm reset and cold reset.

On this reference design, the power-on reset signal is driven from the TPS650250 power management chip. The power management chip will keep the power-on reset signal low until the 1.1V supply has ramped above 1.0V. The warm reset signal is driven high to 3.3V using a pull-up resistor and driven low from a push button. Note the power-on reset signal is a 1.8V signal and the warm reset signal is a 3.3V signal.

The RTC module has a dedicated power-on reset signal (RTC_PWRONRSTn) to reset RTC logic and circuitry during power up. RTC_PWRONRSTn is expected to be driven low when the RTC power supply is ramping up. After the power supply reaches its stable value, the RTC_PWRONRSTn can be de-asserted. The RTC module is not affected by the device PWRONRSTn. Similarly RTC_PWRONRSTn does not affect the device reset.

On the reference design, the RTC power on reset signal is driven by the power on reset signal. Note the RTC power-on reset signal is a 1.8V signal.

Processor Power

The AM3352 device requires multiple voltage rails for powering its ARM CPU, real-time clock (RTC) module, DDR interface, input/output pins, peripheral interfaces, and other internal blocks. In this reference design, the AM3352 is powered using 1.1V, 1.5V, 1.8, and 3.3V voltage rails. The Power Distribution section summarizes the voltages rails used in the reference design and the devices powered by each voltage rail.

The power supplies to the AM3352 device must be ramped to valid voltage levels in a specific order. The power supply sequencing requirements are listed in the AM3352 device data manual. Refer to the Power Sequencing for more information on the power sequencing implementation on this reference design.

The device operating point defines the maximum clock frequency for the ARM CPU, the DDR interface, and various internal clocks in the device. The VDD_CORE supply of the AM332 processor sets the device operating point. On this reference design, the VDD_CORE supply is fixed to 1.1V. This allows the AM3352 processor (ZCE package, revision A) to operate the CPU up to 600MHz and the DDR3 interface up to 400MHz.

IMPORTANT

Always refer to the AM3352 data manual for the latest information on the device operating points.

Memory Interfaces

The reference design supports the following memory devices: DDR3 SDRAM, NAND flash, and SPI NOR flash. The following sections provide more details on the design for each interface.

DDR Memory

The AM3352 processor connects to DDR3 SDRAM devices using a dedicated interface bus which supports JEDEC standard compliant mDDR(LPDDR), DDR2, DDR3, and DDR3L SDRAM devices with a 16-bit data path to external SDRAM memory. The reference design uses a 2-Gbit DDR3 SDRAM device from Micron (part number: MT41J128M16HA-15E:D) with a speed grade of 1333 MT/s. The memory bus supports speeds up to 400 MHz.

NAND Flash

The GPMC bus of the AM3352 processor connects to a 2-Gbit NAND flash memory from Micron (part number: MT29F2G08ABBEAHC). The NAND flash memory is 8-bit wide and operates at 1.8V. To support NAND flash booting, the memory is connected to the GPMC_CSn0 pin for chip select and the GPMC_WAIT0 pin for busy monitoring.

SPI NOR Flash

A 3.3-V 256-Mbit SPI flash memory is supported by the reference design. To support SPI NOR flash booting, the flash memory is connected to SPI0, chip select 0 (SPI0_CS0) on the processor. The SPI flash is from Spansion (part number: S25FL256S).

NOTE

The write-protect and hold pins of the SPI NOR flash are pulled high to 3.3V in the reference design. As a design enhancement, these pins could be connected to available I/O pins on the processor for software control.

NOTE

The reset pin on the SPI NOR flash is pulled high to 3.3V in the reference design. As a design enhancement, this pin could be tied to the push button reset signal to ensure the SPI NOR flash gets reset during a warm-reset.

I2C Configuration EEPROM 

The board contains a serial EEPROM which can be used to store board or system identification information. Software running on the processor could use this data to enable or disable features depending on the data stored in the serial EEPROM. Other hardware specific data can be stored in this memory as well. The part number of the memory device used is CAT24C256W. The I2C EEPROM is connected to the I2C0 port on the processor. The I2C EEPROM is configured for a slave address of 50h.

Gateway EEPROM Data

Name	Size	Contents
Header	4	MSB 0xEE3355AA LSB
Board Name	8	Name for board in ASCII “A335ZBGW” = Gateway reference design
Version	4	Hardware version code for board in ASCII “1.2B” = rev. 01.2B
Serial Number	12	Serial number of the board. This is a 12 character string which is: WWYY4P16nnnn where: WW = 2 digit week of the year of production YY = 2 digit year of production nnnn = incrementing board number
Reserved	32	Reserved for future use
Reserved	6	Reserved for future use
Reserved	6	Reserved for future use
Reserved	6	Reserved for future use
Available	32702	Available space for other non-volatile codes/data

Boot Strap

The SYSBOOT pins of the AM3352 processor control the different boot settings of the device. These pins are latched during a power-on reset. The following table lists the function and setting for each of the SYSBOOT pins. Note that on this reference design some pins are fixed and others are configurable through switch SW2.

NOTE

SYSBOOT pins can be used as I/O pins and connected to other devices in the board. However, care must be taken to ensure the pull-up or pull-down resistors used to set the state of the SYSBOOT pins during reset are not negated by those devices. For example, some devices may include internal pull-up or pull-down resistors on their pins, which may conflict with the resistors controlling the SYSBOOT pins.

SYSBOOT Function and Board Setting

PIN #	FUNCTION	BOARD SETTING
SYSBOOT[15:14]	For all boot modes: Crystal frequency	01b = 24 MHz
SYSBOOT[13:12]	For all boot modes: Reserved	00b
SYSBOOT[11:10]	For XIP boot2: Muxed or non-muxed device For NAND boot: must be 00b	00b
SYSBOOT[9]	For NAND and NANDI2C boot: NAND ECC For Fast External Boot1: must be 0b	0b = ECC done in ROM
SYSBOOT[8]	For XIP boot1: Bus width	0b
SYSBOOT[7:6]	For EMAC boot2: PHY mode	01b = RMII
SYSBOOT[5]	For all boot modes: CLKOUT1 enable/disable	0b = CLKOUT1 disabled
SYSBOOT[4:1]	Boot Mode Select	Configurable through SW2[4:1] See Boot Mode Select section
SYSBOOT[0]	Boot Mode Select	0b

1. XIP boot and fast external boot are not supported on this reference design
2. Reference design only supports RMII mode.

Refer to Boot Mode Selection section for details on selecting a specific boot mode.

RF Design

WiFi Interface

This reference design uses the R078 (WL1837) WLAN/BT wireless module from TDK to enable Wi-Fi and Bluetooth/BLE technology. The R078 module is based on the WiLink8 chip set from Texas Instruments.

The following table summarizes the WiLink8 power, clock, and control/data interface requirements and implementation on the reference design.

WiLink8 Module Requirements

REQUIREMENT	DETAILS	IMPLEMENTATION
Power Supply	3.3V VBAT supply	Supplied from 3.3V main supply.
	1.8V VIO supply	Supplied from 1.8V main supply.
Clocking	32.768 kHz slow clock	Supplied from dedicated 32.768kHz oscillator.
	26 MHz main clock	Supplied from dedicated 26MHz oscillator.
WLAN Control and Data Interface	WLAN_EN (1.8V) control pin	Connected to GPIO3[9] pin (1.8V), pulled down by default through resistor.
	WLAN_IRQ (1.8V) interrupt pin	Connected to GPIO1[30] pin (1.8V), pulled up by default through resistor.
	SDIO (1.8V) data interface	Connected to MMC1 port.
BT Control and Data Interface	BT_EN (1.8V) control pin	Connected to GPIO2[1] (1.8), pulled down by default through resistor.
	UART (1.8V) data interface	Connected to UART1 port (3.3V) through level shifter.
Antenna	Dual antennas for MIMO operation	Two chip antennas (p/n ANT016008CD2442MA1) with option for external antenna support through UF.L connector.

ZigBee Design

This reference design uses the RC2400HP ZigBee-Ready RF transceiver module from Radiocrafts. The RC2400HP module is based on CC2530 ZigBee device from Texas Instruments.

The following table summarizes the CC2530 power, clock, and control/data interface requirements and implementation on the reference design.

CC2530 Module Requirements

REQUIREMENT	DETAILS	IMPLEMENTATION
Power Supply	3.3V VCC supply	Supplied from 3.3V main supply
Control and Data Interface	RESET (3.3V) control pin	Connected to GPIO2[6] pin (3.3V), pulled up by default through internal resistor on CC2530.
	UART (3.3V) data interface	Connected to UART4 port.
Debug Interface	Serial interface for flashing CC2530 firmware	Connected to JP1 5-position jumper; see section JP1, CC2530 Debug Port for details.
Antenna	Single antennas for RF operation	Single chip antenna (p/n ANT016008CD2442MA1) with option for external antenna support through UF.L connector.

ZigBee-WLAN Coexistence Interface

This reference design includes a direct interface between the CC2530 and the WiLink8 WLAN module to allow both radios to coexist with each other. During heavy WLAN traffic, the CC2530 can request for a break in WLAN activity such that it can send and receive ZigBee packets. When the request is received the WLAN module can gracefully create a break in its RF activity.

The following table provides more information on the ZigBee-WLAN coexistence interface.

A level shifter is used to interface both radios since the CC2530 pins operate at 3.3V while the WiLink8 WLAN pins operate at 1.8V.

NOTE

The ZigBee-WLAN coexistence interface is currently not supported by WiLink8 and CC2530 firmware.

ZigBee-WLAN Coexistence Interface

PIN NAME	FUNCTION	DETAILS
COEX_MWS_ACTIVE	PA_SHUTDOWN	CC2530 to WLAN pin. Request for break in WLAN traffic.
COEX_MWS_BT_WL_TX_O	TX_ACTIVE	WLAN to CC2530 pin. Indicates WLAN TX activity.
COEX_MWS_RX_PRI	RX_ACTIVE	WLAN to CC2530 pin. Indicates WLAN RX activity
COEX_MWS_FRAME_SYNC	Reserved for future use	Reserved for future use

Peripheral Interfaces

USB Host Port

One USB host port is supported on the reference design. The USB0 port on the processor is connected to a standard A connector. The ESD device TPD4S012 and common choke filter ACM2012 (TDK) are used on the USB signals before they are connected to the AM3352 pins. A current-limited power distribution switch (part number: TPS2051B) provides a 5V VBUS output to the USB connector. The power distribution switch is enabled by the USB port on the processor through the USB0_DRVVBUS pin.

NOTE

For proper operation, USB firmware running on the processor must be allowed to enable/disable the VBUS voltage. For this reason, a power distribution switch is used instead of driving the VBUS voltage directly from the 5V supply to the board. A field-effect transistor (FET) could also be used to gate the 5V supply from the VBUS pin.

10/100 Ethernet Port

The reference design has one 10/100 Ethernet transceiver (PHY) from Texas Instruments (P/N: DP83848J). The Ethernet PHY is reset through the push button on the board. The PHY can also be reset by software through an I/O pin on the AM3352 processor. A 50-MHz oscillator drives the reference clock signal for the PHY and the processor.

Power System Design

PMIC Selection

There are multiple methods for generating the different voltage rails in an AM3352-based design. A power management device (PMIC) provides a convenient method to provide power to the AM3352 processor and the other logic on the board since it integrates multiple LDOs and DCDC converters in a single package. The PMIC can also provide a reset signal and, in some cases, a run-time programmable supply to support different voltage and frequency operating points.

The TPS650250 power management device is used to supply most of the power rails required by this design. The TPS650250 provides three highly efficient, step-down converters targeted at providing the core voltage, peripheral, I/O and memory rails in a processor based system. All three step-down converters enter a low power mode at light load for maximum efficiency across the widest possible range of load currents. The converters can be forced into fixed frequency PWM mode by pulling the MODE pin high.

The TPS650250 also integrates two general purpose 200mA LDO voltage regulators, which are enabled with an external input pin. Each LDO operates with an input voltage range between 1.5V and 6.5V allowing them to be supplied from one of the step-down converters or directly from the battery. The output voltage of the LDOs can be set with an external resistor divider for maximum flexibility. Additionally there is a 30mA LDO typically used to provide power in a processor based system to a voltage rail that is always on.

Power Distribution

There are six main power rails for powering the logic on the reference design. The TPS650250 power management chip (PMIC) supplies most of the power rails for the reference design. The TPS2051B power-distribution switch provides power for the USB VBUS supply. The following table summarizes the power rails and their loads.

Reference Design Power Rails

RAIL	LOAD	SOURCE	SOURCE MAX OUTPUT CURRENT (mA)	RAMP ORDER
VDDS_CORE_1V1	AM3352 Core	PMIC DCDC3	800	3
VDDS_ANA_1V8	AM3352 ADC, PLL, USB	PMIC LDO1	200	1
VDDS_MAIN_3V3	SPI NOR, AM3352 I/O, USB, Ethernet PHY, LEDs, WiLink8 VBAT, TXCO LDO, USB-to-serial, CC2530, EM Expansion, I2C EEPROM, VTT LDO, PLC Expansion	PMIC DCDC1	1600	2
VDDS_IO1_1V8	AM3352 I/O, NAND, WiLink8 I/O, 32.768kHz oscillator	PMIC LDO2	200	1
VDDS_DDR3_1V5	AM3352 DDR I/O, DDR3 SDRAM, VTT LDO	PMIC DCDC2	800	1
USB0_VBUS	USB VBUS	USB Switch	500	Disabled by default

Power Sequencing

The power supplies to the AM3352 device must be ramped to valid voltage levels in a specific order. The power supply sequencing requirements are listed in the AM3352 device data manual. In this reference design the TPS650250 power management device is wired to ramp its 1.8V and 1.5V supplies first, followed by the 3.3V supply, and lastly the 1.1V supply (see section Power Distribution). The 5V VBUS supply is powered off by default and must be enabled through software.

Physical Description

Board Layout

The Gateway reference design is a 3040Wx 3625L mils (72.2 x 92.1 mm) 8-layer printed circuit board. The figures below show the layout of the board.

Board Layout (Top)

Board Layout (Bottom)

Switches

The reference design has multiple switches which control features such as boot mode and reset. The following sections provide more details on the switches used in the reference design.

S1, Warm Reset

The warm reset is generated from a push button. The warm reset is driven high to 3.3V using a pull-up resistor and driven low when the push button is pressed. The warm reset affects the AM3352 WARMRSTn pin and the 10/100 Ethernet PHY RST# pin.

NOTE

SYSBOOT pins are not latched with a warm reset. The processor will boot with the SYSBOOT values from the previous power-on reset.

SW2, Boot Mode Selection

Switch SW2 controls the ROM boot mode sequence of the AM3352 processor. The table below lists the switch settings for the boot modes supported by the reference design. The figure below shows the ON and OFF positions of SW2.

NOTE

For each boot mode setting, the ROM cycles through four different boot modes. For more information on each boot mode refer to the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73).

SW2, Boot Mode Select

SW2:4 SYSBOOT4	SW2:3 SYSBOOT3	SW2:2 SYSBOOT2	SW2:1 SYSBOOT1	SYSBOOT01	BOOT SEQUENCE
ON (0)	ON (0)	ON (0)	OFF (1)	1	UART0	SPI0	XIP	MMC0
OFF (1)	ON (0)	ON (0)	OFF (1)	1	NAND	NANDI2C	MMC0	UART0
OFF (1)	ON (0)	OFF (1)	OFF (1)	1	MMC0	SPI0	UART0	USB0
OFF (1)	OFF (1)	ON (0)	ON (0)	1	SPI0	MMC0	EMAC1	UART0

1. SYSBOOT0 is connected to ZigBee reset which has an internal pull-up. This overrides 100k pull-down on board and forces SYSBOOT0 = 1b.

Boot Selection

Jumpers

The reference design has several jumpers which are used to access specific points in the design. The following sections provide more details on the jumpers used in the reference design.

JP1, CC2530 Debug Port

The jumper JP1 interfaces to the CC2530 debug port. With the use of an external programmer, the debug port can be used flash firmware to the CC2530 device. The following table gives the pin out of the JP1 connector.

JP1, CC2530 Debug Port Pin Out

PIN #	SIGNAL
1	CC2530 DC
2	BOARD 3.3V
3	CC2530 DD
4	BOARD GND
5	CC2530 RESET

JP2, External Power

Jumper JP2 can be used to connect a 5V DC supply directly into the board.

NOTE

Any DC supply used with the reference design must be capable of providing up to 12W of power to the board.

JP3, WiLink8 Debug Port

Jumper JP3 gives access to the debug port on the WiLink8 device.

JP3, WiLink8 Debug Port Pin Out

PIN #	SIGNAL
1	WL_RS232_TX
2	WL_RS232_RX
3	WL_UART_DBG
4	UART_DEBUG

Connectors

The reference design has several connectors for interfacing to various peripherals, providing board power, and accessing expansion ports. The following sections provide more details on the connectors used in the reference design.

P1, JTAG

This connector supports a 14-pin JTAG emulator. The JTAG pins are directly connected to the AM3352 processor.

NOTE

Some emulators support a target-disconnect signal (TDIS). The TDIS signal is used by the emulator determine if the target cable is physically connected. To support this feature the TDIS signal should be connected directly to the board ground. By default the TDIS pin is not grounded on the board and some emulators (e.g. Blackhawk and XDS100v2 emulators) may report an error when connecting to the board. To support these emulators place a 0 Ohm resistor on R7 to connect the TDIS signal directly to board ground.

P2, PLC Expansion

For future expansion into power-line communication, the reference design connects a few I/O pins and a UART interface to a connector. The pin out for the PLC expansion connector, P2, is given in the following table.

PLC Expansion Connector Pin Out

PIN #	SIGNAL	PIN #	SIGNAL
1	3.3V	2	GND
3	UART3_TXD	4	UART3_CTS
5	GPIO2[13]	6	UART3_RXD
7	GPIO2[12]	8	UART3_RTS
9	NC	10	NC
11	GPIO0[11]	12	GPIO0[10]

P4, P5, EM Expansion

The reference design includes a set of EM expansion connectors, P4, and P5. The EM expansion connectors can be used to add different RF devices to the reference design. The following table gives the full pin out for the EM expansion connectors.

EM Expansion Connector Pin Out

P4				P5
PIN #	SIGNAL NAME	PIN #	SIGNAL NAME	PIN #	SIGNAL NAME	PIN #	SIGNAL NAME
1	GND	2	NC	1	NC	2	GND
3	GPIO2[10]	4	NC	3	NC	4	GND
5	GPIO2[11]	6	UART5_TXD1	5	NC	6	GND
7	UART5_TXD	8	UART5_RXD1	7	3.3V	8	NC
9	UART5_RXD	10	GPIO2[25]	9	3.3V	10	NC
11	NC	12	GPIO0[19]	11	NC	12	NC
13	NC	14	SPI0_CS0N	13	GPIO0[10]	14	NC
15	NC	16	SPI0_CLK	15	GPIO2[23]	16	NC
17	NC	18	SPI0_D1 (MOSI)	17	NC	18	GPIO2[24]
19	GND	20	SPI0_D0 (MISO)	19	GPIO2[22]	20	GPIO0[11]

1. Must be enabled through 0-Ohm resistor (see schematics for more information).
   

J1, Ethernet

The J2 connector provides a 10/100 Ethernet port. The Ethernet port uses a standard RJ-45 connector. The DP83848J Ethernet PHY drives the LEDs on the connector to report link status.

J2, 5-V DC Input Power

Connector J2 is the primary power source to the reference design. This connector provides 5V DC to the board. An external, 5V, 15W power supply should be used with this reference design.

External Power Supply Requirements:

• Nominal Voltage: 5.0 VDC
• Max Current: 3.0 A
• Efficiency Level V

NOTE

TI recommends using an external power supply that complies with applicable regional safety standards such as (by example) UL, CSA, VDE, CCC, PSE, etc.

J3, Serial-to-USB

The connector J3 provides a USB device interface for debugging applications running on the AM3352 processor. The reference design uses a serial-to-USB chip from FTDI to connect the UART0 port on the processor to a USB serial interface. When J3 is connected to a PC/workstation, the drivers for the serial-to-USB FTDI chip will automatically install. Configure the serial application used on the PC/workstation with the settings shown in the following table.

NOTE

If the PC/workstation does not automatically detect and install the correct drivers, download and install the VCP drivers from http://www.ftdichip.com.

Serial Application Settings

OPTION	SETTING
Baud Rate	115200
Data	8 bits
Stop Bits	1 bit
Parity	None
Flow Control	None

J4, USB Host Port

This connector can be used for USB Host functionality. The USB0 port on the AM3352 processor is used for this interface.

J5, J6, J7 External RF Antenna

The reference design includes three UF.L connectors for testing with external antennas. There are three connectors on the reference design as shown in the following table.

External RF Antenna Connectors

CONNECTOR	RADIO
J5	WiLink8 Antenna 1
J6	CC2530 ZigBee
J7	WiLink8 Antenna 2

To use an external antenna, depopulate the 0-Ohm resistor connecting the radio to the on-board chip antenna, and populate the 0-Ohm resistor connecting the radio to the UF.L connector. Refer to the reference design schematics for more details.

User LEDs

There two user LEDs on the reference design, D12 and D13. The user LEDs are driven through I/O pins on the AM3352 processor. The following tables show the I/O control pins and settings to turn the user LEDs on and off.

User LED (D12) Control

GPIO1[14]	GIPO1[15]	STATE
0	0	RED
0	1	GREEN
1	0	RED
1	1	OFF

User LED (D13) Control

GPIO0[22]	GIPO1[31]	STATE
0	0	RED
0	1	GREEN
1	0	RED
1	1	OFF

Additional Information

Board Design Information

Schematics, layout, and BOM file can be obtained from the TI design page for the Smart Home and Energy Gateway reference design (TIEP-SMART-ENERGY-GATEWAY).

Board Revisions

Different revisions of the board are marked as shown in the table below. 

Board Revisions

Board Revision	Board Marking
B	Rev PCB/SCH 0.50/0.54

Known Issues

The following table describes the known design issues with the Gateway.

Advisory List for Smart Home and Energy Gateway

Advisory Number	Revisions Affected	Description	Details	Workaround
1.2	B	Pulldown on SYSBOOT15 negated when using RF430CL330HTB daughtercard	100KOhm pulldown is negated by stronger pullup on RF430CL330HTB daughtercard	Replace R111 on the Gateway with stronger pulldown (e.g. 10Kohm).
1.3	B	SPI chip select does not map to SPI chip select on RF430CL330HTB daughtercard	SPI chip select on the RF430CL330HTB can be controlled through either a GPIO pin or the chip select pin on the AM335x SPI port. Existing board design assumed GPIO pin will be used. For ease of software development, the chip select of the SPI port should be used.	Short pins 6 and 14 on connector P4 of the Gateway or connector RF1 of the RF430CL330HTB daughtercard.
1.4	B	Gateway cannot communicate in SPI mode with RF430CL330HTB daughtercard	RF430CL330HTB can operate in I2C mode (default) or SPI mode. The Gateway uses SPI mode to communicate with the EM header (P4 and P5).	Remove resistor R8 on the RF430CL330HTB daughtercard to enable SPI mode.
1.5	B	Gateway cannot communicate with certain emulators	Some emulators support a target disconnect signal (TDIS). The TDIS signal is used by the emulator determine if the target cable is physically connected. To support this feature the TDIS signal should be connected directly to the board ground. By default the TDIS pin is not grounded on the board and some emulators (e.g. Blackhawk and XDS100v2 emulators) may report an error when connecting to the board.	Place a 0 Ohm resistor on R7 to connect the TDIS signal directly to board ground.