Sitara Layout Checklist

Purpose

This document describes the basic PCB Routing Guidelines required and recommended for the layout of ARM MPU Processor based PCB designs. However, many of these guidelines are generally preferred for other devices as well.

Stackup

The PCB stackup should be designed based on input from the PCB layout person as well as the board fabricator. Overall cost, material type, mechanical, and signal characteristics help determine the stackup for a given PCB.

In most ARM MPU processor based PCB designs, a good solid ground plane is required due to the fast switching signals that are on the board. Therefore, a minimum of 4 layers is usually required for a PCB stackup. Furthermore, impedance control for interfaces such as DDR2 SDRAM, RGMII, and USB will require a particular layer and trace construction methodology.

Placement

The placement of the ARM MPU processor is critical for achieving optimal routing results. Care should be taken to place the processor as well as the other subsystem components in the proper positions to reduce: unintended stubs on traces, wasted and excessive routing, improper routing channels for critical signals.

Therefore, it’s a good practice to do a preliminary high level placement diagram to optimally plan the location of key components (including connectors) with regard to spatial concerns.

Source Termination

Many interface signals will require a source termination resistor to attenuate reflection signals. These source termination resistors should be placed as close to the driving element’s pin as possible. While PCB simulation results can be used to yield a more exact value for this termination resistor based on a specific PCB layout, rough standard values such as 22 or 33ohms can be used for initial design.

Crystal/Oscillator

Crystals used for clock generation are often used to drive PLL’s and are thus sensitive to jitter from noise, temperature, and power supply changes. Be sure to minimize routing to crystal and other clock sources.

Power Components

With the rise in current requirements, it is important to place power components in locations that allow appropriately sized conductors to and from the power sources.

Decoupling Capacitors - Processor

Decoupling capacitors are critical for proper voltage regulation to the processor to minimize voltage changes that occur as a result of dynamic energy changes. It is important, therefore, to place several of the small decoupling capacitors such as 10nF capacitors as close to the processor power supply pins as possible. Look at the data sheet of the processor to see the higher concentration of power supply pins. These power supplies will generally demand higher amounts of current and thus can benefit from a greater share of the overall pool of decoupling capacitors.

When planning the escape routing of the processor, keep in mind that the power distribution network (PDN) is responsible for supplying all power in and out of the processor. Therefore, it should be planned with adequate space for placing decoupling capacitors close to the appropriate power supply pins.

Routing

Signal nets should be sorted into a prioritized list so that the high speed and critical signals can be identified. Routing the highest priority signals and power first will ensure that the signal characteristics required by these critical nets are met.

Power Supplies

Power nets should be analyzed to see if a split (or full) plane is required or a trace is adequate. Ground nets need to be used for return signal paths so usually an entire plane (or two for 6 layer boards) is required. Usually running the significant power supplies first allows better planning of the use of the available copper layers. Core type power supplies will usually demand the most current from the main power source so it is important to reserve enough copper on the power plane(s) for the core power supplies. Also, certain I/O groups such as DDR2 SDRAM will have fast switching cells that require a low impedance power path to maintain a solid voltage level. Any layer changes should be looked at to determine if more than one via is necessary to maintain the low impedance path.

LCD Signals

Parallel LCD signals usually travel a fair distance (> 2-3in) and they are mostly referenced to the single pixel clock signal. Therefore, as the frequency of the pixel clock rises it becomes more important to keep the integrity of the LCD pixel clock as high as possible so that the timing constraints are not violated on the receiving end.

These signal traces should be length matched to guarantee similar flight time to the receiving end. Although impedance matching may not be necessary, controlling them to 50ohms single ended will help provide a more stable timing margin for clocking the data signals. A solid and continuous ground plane should be built on the adjacent layer to these signals.

DDR2 SDRAM Signals

DDR2 SDRAM signals are particularly prone to noise, skew, and jitter which will all affect the timing margins of the signals with respect to the clock and consequently the overall max throughput that can be achieved. The SDRAM devices should be placed close to the processor with adequate routing channels to place the signal traces in between the processor and the SDRAM packages. The traces should be controlled to 50ohm signal ended impedance for the length of the traces with solid reference planes on the adjacent layer. The differential pairs such as clk/clkn and dqs/dqsn should be run with controlled impedance of differential 100ohms.

When two or more SDRAM packages are used to connect to the same DDR2 SDRAM bus, then the signals which run to both packages should be routed in a T architecture with the short legs of the T to each SDRAM package having the same length to minimize the reflection effects. Be careful not to run other high speed signals from other non-SDRAM busses across the area where the DDR2 SDRAM signals are routed as crosstalk from these aggressor nets can affect the signal characteristics of the DDR2 SDRAM signals. All the SDRAM signals should be length matched to the clk/clkn signal pair length average. The clk/clkn signals should be length matched to each other to within 10mils.

USB Signals

As defined by the USB Specification, USB data signals must be routed as 90ohm controlled differential traces. These signals must also have length matched traces. Also, there should be a solid and continuous ground plane adjacent to these signals the entire length of the trace. Keep other high speed signals away from these USB signals.

Ethernet PHY Signals

Ethernet PHY signals relating to the MII or RMII bus are fairly low speed but still should be routed with care to be sure that the RXCLK and TXCLK and their associated data signals have a solid ground reference underneath them and they should be length matched.

RGMII bus signals have additional requirements due to their freq of operation and signal transition time requirements. These signals should be routed with care with a solid ground plane underneath them. If possible they should be routed on the top or bottom layers of the board to allow max propagation speed. Keep other signals, especially signals such as clocks with many level changes, away from these signals by at least 12 to 15mil. These signals should be have their impedance controlled to 50ohms single ended. If possible, route ground guard traces co-planar to the clock traces.

Analog ADC Signals

Analog signals in general are subject to attenuation because of the lack of a level margin for the functional operation. Therefore, the traces carrying these signals must be free from crosstalk from neighbor traces. Keep other high speed signals and high power signals away from these ADC signals.

General Guidelines

Generally, minimize the number of vias in signals. When routing signals, keep the direction changes to more rounded cornering than hard, point cornering. Identify key signals that need distance requirements so that their traces can be routed within short spaces.

Current Return Path

Each signal must have a valid return path. Many signals have slow edge rate transitions or have relatively slow timing parameters. These types of signals can use ground return paths that are not carefully planned out because any perturbations arising in the signal do not affect the signal’s function enough to cause failures in the system. However, higher speed signals and signals with tighter timing constraints benefit greatly with an adjacent ground plane or trace as it reduces the return current loop. Furthermore, for signals that require controlled impedance, it is very difficult to maintain a consistent impedance on the trace without a reference plane.

If a reference plane is used for the current return path, it is important to keep layer changes (and thus transitions through vias) to a minimum. Also, the same reference plane should be used for the entire distance of the signal or impedance mismatches will occur across the boundaries of the different references. If two or more reference planes are used (ground or power), be sure to stitch the multiple planes together with multiple vias to provide multiple opportunities for current paths.

Coplanar Trace Spacing

When signals travel next to each other, one aggressor net may induce a portion of it’s signal into the adjacent victim trace especially if they run parallel to each other (horizontally or vertically). This crosstalk can adversely affect the signal in the victim net. Keep standard trace width values for each particular net based on the characteristics of each net. Be sure to keep the co-planar spacing to a safe value (2w where w = trace width) to minimize crosstalk between two adjacent traces.

Trace Length Matching

Signals that belong to the same bus group may need to have their traces matched in overall length to guarantee that their difference in flight time will not adversely affect the timing constraints of the interface. To be accurate, each interface should be reviewed for the worst case AC timing parameters and the expected signal edge transition time. Then the maximum deviation in trace length can be calculated based on the

Differential Routing vs Single ended Routing

Signals that are differential should be treated with extra care to maintain the strong coupling effects of the differential pair. The inter-trace gap should be kept to a constant value. Also, these traces should not run parallel to a clock or other rapidly changing signal trace. Minimize the number of vias on the differential signal traces. When entering and exiting a pad (termination or device), keep the same entry geometry for both signals in the pair. The length should be matched between the signal and inverted signal within the differential pair.