Simulator Cycle Accuracy

Simulator Cycle Accuracy

TI provides cycle accurate simulator as part of Code Composer Studio. These cycle accurate simulators are needed for architectural explorations, performance analysis & application code tuning.

Cycle Accuracy improvements

In recent time we have done a lot cycle accuracy improvement on C64x+ & ARM simulator as the deviation reported were huge on device simulator.

Cycle accuracy improvement was planned to be achieved by ensuring Transaction/Behavioral Accuracy & Latency Accuracy across all levels. Test suite was created to include all the data flow path and cycle number are compared with QT or RTL for accuracy. Later simulator models were fine tuned for accuracy based on the results.

Cycle Accuracy Results on C64x+

Path/Scenario	Modules involved	Accuracy (reference platform: QT)
CPU based memory accesses	C64x+ CPU, GEM memory system, VBUSM-SCR, DDR3	Average deviation < 4%
CPU based Configuration address space accesses	C64x+ CPU, GEM memory system, VBUSP-SCR, Peripheral	Average deviation < 6%
DMA based memory accesses (for large sized transfers)	EDMA (CC and TC), VBUSM-SCR, DDR3, GEM internal memory path	Average Deviation < 6%
DMA based memory accesses (for small sized transfers)	EDMA (CC and TC), VUSM-SCR, DDR3, GEM internal memory path	Average Deviation < 12%
Full application	C64x+ CPU, GEM memory system, VBUSM-SCR, VBUSP-SCR, EDMA (CC and TC), DDR3, VCP2	Deviation: Peak load < 0.1% Average load < 0.9%

Cycle Accuracy Results on ARM/Cortex-M3

Configuration	Reference platform	Tests Used	Accuracy achieved
ARM9e CPU Cycle Accurate Simulator	Verified against ARM Ltd’s cycle accurate simulator (ARMulator)	Verified for ARM Core validation tests	< 5% deviation
Cortex-M3 CPU Cycle Accurate Simulator	M3 RTL	Verified for automotive applications and M3 core validation tests	< 5% deviation

Configuration Applicable

Cycle accuracy improvments is applicable for the following list of configurations.

• All C64x+ devices Simulator
• ARM9 & Cortex-M3 Simulator

All the above cycle accuracy improvement will be available on CCSv3.3 SR12.

Configuring the simulator to match a particular HW board (description for CCSv3.3)

The same chip can be operated in different HW configurations, which influence device performance. These include the following factors.

• CPU MHz
• Ext. memory MHz
• Ext. memory width
• Ext. memory timings

These settings will have to be matched for the simulator to model a particular hardware board accurately.

To adjust the first three items in above list, a simulator .cfg file needs to be edited. There is no GUI support for this in CCSv3.3. The file format is not documented, but the following steps show the settings that can be adjusted for C6000 chips (taking the example of a DM6437 board).

• Open cc_setup.exe.
• In the System Configuration column, select the chip symbol (leaf in the configured tree) underneath the simulator you have configured (e.g. "TMS320C6400_0" for a "DM6437 Little Endian Simulator").
• Right-click -> Properties...
• Note the path and .cfg file name which is configured under the "Simulator Config File" entry (e.g. "C:\CCStudio_v3.3\drivers\simdm6437.cfg").
• Make a backup copy of this file.
• Edit it in a text editor and apply the following adjustments:
  • Search for "cpu_clk_freq" and configure the board's CPU frequency there (e.g. to 594).
    • Note that there may be multiple occurrences of "cpu_clk_freq" and the other keywords which are mentioned in the below bullets. It would be important to identify the correct MODULE section which applies to the considered memory interface (e.g. "MODULE EMIFB" for C6455's DDR2).
  • The "vbus_clk_freq" should be adjusted accordingly, to retain the same rate vs. "cpu_clk_frequency" (e.g. original "vbus_clk_freq" 200 / original "cpu_clk_freq" 600 * new "cpu_clk_freq" 594 = 198).
  • Adjust the "mem_clk_freq" according to the DDR2 clock frequency of the board (just for clarity: the DDR2 clock frequency is 1/2 the Mtransactions/s).
  • If 32-bit DDR2 are populated on the board, keep "narrow_mode" at 0; if only 16-bit DDR2 are available on the board set "narrow_mode" to 1.

In the simulated target program, make sure to have the DSP program write to (initialize) the DDR2 peripheral's timing registers, as the simulator will use these timings to model the external memory accesses.

FAQ

• Q: What is the cycle accuracy of F28x Simulator?

Refer the F28x datasheet for cycle accuracy results - sprs466.pdf

• Q: Is the cycle accuracy improvement applicable for C64xx simulators?

No, the above cycle accuracy improvements are not applicanble. For cycle accuracy results on C64xx simulator refer - spru600i.pdf document.