Simulator Analysis Event Description

C6000 Simulator Analysis Events Description

The C6000 simulator analysis event description is available in this page.

Cycle Events

Event Name	Description
cycle.CPU	A CPU cycle consumed This event includes instruction execution cycle , cross path stalls and memory bank conflict stalls. This does not include memory-access stalls (except the L1D memory bank conflict stalls in the case of Functional Simulator)
cycle.Total	This event count includes instruction execution cycle count, all stalls (including pipeline stalls), memory latency and system effects.

CPU Events

Event Name	Description
CPU.access.data.read	Data read access from CPU
CPU.access.data.write	Data write access from CPU
CPU.access.summary	Data read or write access from CPU
CPU.discontinuity.branch	A discontinuity (or jump) occurred in the PC value due to the execution of a branch instruction.
CPU.discontinuity.interrupt.summary	A discontinuity (or jump) occurred in the PC value due as a result of an interrupt taken
CPU.discontinuity.summary	PC discontinuity.
CPU.execute_packet	An execuet-packet decoded.Event will be reported against the address of the first instruction.
CPU.instruction.decoded	An Instruction decoded
CPU.instruction.executed	An instruction executed
CPU.instruction.condition_false	The Predicate for the instruction evaluated to false
CPU.NOP	No-Operation cycles executed.
CPU.idle	CPU idle cycles (IDLE instuction)
CPU.stall.mem.L1P	Stall cycles due to L1P accesses.
CPU.stall.mem.L1D	Stall cycles due to L1D accesses (e.g. L2 SRAM access missing in L1D).
CPU.stall.mem.bank_conflict	Stall cycles due to bank conflicts.
CPU.stall.mem	= CPU.stall.mem.L1P + CPU.stall.mem.L1D + CPU.stall.mem.bank_conflict.
CPU.stall.crosspath	Stall cycles due to Cross Path data access.
CPU.stall.summary	= CPU.stall.mem + CPU.stall.crosspath.

Miscellaneous events not exposed by default

These events are available on C64x+, C647x, miniC64 and C66x ISAs.

In order to enable below set of events (IPC and functional unit utilization),

User has to edit the simulator configuration file and add the line POWER_PROFILING ON; To do this, search for TYPE CPU; line and add the power profiling line after that.

For eg., if using on TCI6616 simulator, open the tisim_tci6616.cfg from simulation*/bin/configurations area.

MODULE CPU0;

  ....

 TYPE CPU;

 POWER_PROFILING ON;

  ...

END CPU0;

IPC events

Event Name	Description
CPU.IPC_Cycles.ipc_of_0	0 Instruction per cycle
CPU.IPC_Cycles.ipc_of_1	1 Instruction per cycle
CPU.IPC_Cycles.ipc_of_2	2 Instruction per cycle
CPU.IPC_Cycles.ipc_of_3	3 Instruction per cycle
CPU.IPC_Cycles.ipc_of_4	4 Instruction per cycle
CPU.IPC_Cycles.ipc_of_5	5 Instruction per cycle
CPU.IPC_Cycles.ipc_of_6	6 Instruction per cycle
CPU.IPC_Cycles.ipc_of_7	7 Instruction per cycle
CPU.IPC_Cycles.ipc_of_8	8 Instruction per cycle

Functional unit utilization events

Event Name	Description
CPU.func_unit_cycles.L1	Instructions(cpu cycles) executed on L1 unit
CPU.func_unit_cycles.M1	Instructions(cpu cycles) executed on M1 unit
CPU.func_unit_cycles.S1	Instructions(cpu cycles) executed on S1 unit
CPU.func_unit_cycles.D1	Instructions(cpu cycles) executed on D1 unit
CPU.func_unit_cycles.L2	Instructions(cpu cycles) executed on L2 unit
CPU.func_unit_cycles.M2	Instructions(cpu cycles) executed on M2 unit
CPU.func_unit_cycles.S2	Instructions(cpu cycles) executed on S2 unit
CPU.func_unit_cycles.D2	Instructions(cpu cycles) executed on D2 unit

Cache Events

Event Name	Description
L1D.hit.read	CPU read access is a hit in L1D
L1D.hit.write	CPU write access is a hit in L1D
L1D.hit.summary	Total hits in L1D Cache
L1D.miss.read	CPU read access is a miss in L1D
L1D.miss.write	CPU write access is a miss in L1D
L1D.miss.summary	Total misses in L1D Cache
L1D.access	All data accesses from CPU to L1D
L1D.miss.conflict	L1D cache miss due to conflict (a miss is said to be of type conflict if the access is a miss in the actual cache, whereas it would have been a hit in a fully associative cache of the same size)
L1D.miss.non_conflict	L1D cache miss that is not due to conflict (such misses are either cold misses or capacity misses)
L1D.miss.non_cacheable	L1D miss due to an access whose address is in a non-cacheable region (due primarily to the MAR register settings)
CPU.stall.mem.L1D	CPU stall cycles due to L1D
L1D.stall.write_buf_full	A write buffer exists between the L1D and L2 caches. There can be up to four non-mergeable write misses outstanding in the write buffer without stalling the CPU. If a write miss occurs when the write buffer is full, this event will occur.
L1P.hit	L1P cache hit
L1P.miss.summary	Total L1P cache misses
L1P.access	all program fetches from CPU to L1P
L1P.miss.conflict	L1P cache misses that are conflict misses (a conflict miss is a miss in the actual cache, whereas the access would be a hit in a fully associative cache of the same size)
L1P.miss.non_conflict	L1P cache misses that are not due to conflicts (a non conflict miss is either a cold miss or a capacity miss)
L1P.miss.non_cacheable	L1P cache miss due to an access whose address is in a non-cacheable region (due primarily to the MAR register settings)
CPU.stall.mem.L1P	CPU stall cycles due to L1P
L2.cache.hit.data.read	L2 cache hits for L1D read requests
L2.cache.hit.data.write	L2 cache hits for L1D write requests
L2.cache.hit.prog	L2 cache hits for requests from L1P
L2.cache.hit.summary	Total L2 Cache hits for requests from L1D and L1P
L2.cache.hit.data.summary	Totol L2 cache hits for requests from L1D
L2.cache.miss.data.read	L2 cache misses for read requests from L1D
L2.cache.miss.data.write	L2 cache misses for write requests from L1D
L2.cache.miss.prog	L2 cache misses for requests from L1P
L2.cache.miss.summary	Total L2 cache misses for requests from L1D and L1P.
L2.cache.miss.data.summary	Total L2 cache misses for requests from L1D
L2.cache.miss.conflict	L2 cache misses that are of type conflict ( a miss is said to be a conflict miss if the access is a miss in the actual cache, whereas it would have been a hit in a fully associative cache of the same size)
L2.cache.miss.non_conflict	L2 cache misses that are not due to conflict (such misses are either cold misses or capacity misses)
L2.cache.miss.non_cacheable	L2 cache misses for requests whose addresses are in non-cacheable regions (due primarily to MAR register settings)
L2.cache.access	Total L2 cache requests from L1D and L1P
L2.SRAM.data.read	L1D read from L2 SRAM
L2.SRAM.data.write	L1D write to L2 SRAM
L2.SRAM.data.summary	Total L1D accesses to L2 SRAM
L2.SRAM.prog	L1P read from L2 SRAM
L2.SRAM.dma.read	DMA Read access to L2 SRAM
L2.SRAM.dma.write	DMA Write access to L2 SRAM
L2.SRAM.dma.access	DMA access to L2 SRAM
L1P.victim	L1P miss caused a victim in L1P (a L1P victim is caused by an L1P miss requiring eviction).
L1P.snoop.hit	L2 snoop request that is a hit in L1P
L1P.snoop.hit.victim	L1P snoop hits caused due to L2 victim
L1P.snoop.hit.dma	L1P snoop hits caused due to DMA access to L2 SRAM
L1P.snoop.hit.cache_control_op	L1P snoop hits caused due to cache control operations (flush, write back operations to L2)
L1P.snoop.miss	L2 snoop requests that miss L1P
L1P.snoop.summary	Total snoops to L1P (misses, clean hits, dirty hits)
L1D.victim.dirty	L1D victims that are dirty (that is, eviction of a line that has been modified)
L1D.victim.summary	Total L1D victims (a L1D victim is caused by an L1D miss requiring eviction).
L1D.snoop.hit.summary	L2 Snoop request that is a hit in L1D
L1D.snoop.hit.victim	L1D snoop hits caused due to L2 victim
L1D.snoop.hit.dma	L1D snoop hits caused due to DMA access to L2 SRAM
L1D.snoop.hit.cache_control_op	L1D snoop hits caused due to cache control operations (flush, write back operations to L2)
L1D.snoop.hit.dirty	L1D snoop hit to an L1D line that has been modified
L1D.snoop.hit.dirty.victim	L1D snoop hits to dirty lines caused due to L2 victim
L1D.snoop.hit.dirty.dma	L1D snoop hits to dirty lines caused due to DMA access to L2 SRAM
L1D.snoop.miss	L2 snoop request that is a miss in L1D
L1D.snoop.summary	Total L1D snoops (misses, clean hits, dirty hits)
L1D.miss.write_merge	A write buffer exists between the L1D and L2 caches. The write buffer allows merging of write requests. It merges two write misses into a single transaction provided the following rules are obeyed: The double-word address of the two accesses is the same; the two accesses are to L2 configured as SRAM; the oldest write has just been placed in the write buffer queue; the newest write has not been placed in the buffer queue
L2.cache.victim.dirty	Victimized line in L2 has been modified (needs to be saved to corresponding memory locations)
L2.cache.victim.data	L1D access caused victim in L2
L2.cache.victim.prog	L1P access caused victim in L2
L2.cache.victim.summary	L2 access that causes a L2 victim (victim is caused by a miss requiring line eviction)