Setting up OMAP35x SDRC registers

Introduction

The following information describes how to set the SDRC registers in the OMAP35x SDRC module depending on the mDDR memory that you are using. Both 16-bit and 32-bit mDDR configurations are addressed in this wiki.

CS specific registers

Each of these registers are defined for each chip select (CS0 and CS1). If you are using both chip selects, ensure that you set both register accordingly. If you are using only CS0, CS1 register can be left in their default state.

• SDRC_MCFG_p - The value in this register will depend a lot on your memory configuration. Here are some tips to configure each value:
  
  • LOCKSTATUS - This bit should remain 0 for full use of the MCFG register.
  • RASWIDTH, CASWIDTH - these values depend on the configuration of the memory. Most memory datasheets will define how many row address bits and column address bits are used. You can use these values to set these 2 bit field. Also in the TRM, there are examples in the table entitled “SDRC Address Multiplexing Scheme Selection vs SDRAM Configurations” (there is a table for 32 bit or 16 bit memory interface). Determine the configuration of your memory (eg. 64M x 32) and total size (eg, 2048Mbits) to conclude how many row and column address bits to set. In this example, 10 column bits and 14 row bits. So RASWIDTH = 0x3, CASWIDTH = 0x5.
  • ADDRMUXLEGACY - should always be set to 1 in order to use RASWIDTH and CASWIDTH as described above.
  • RAMSIZE - total capacity of memory, divided into 2MByte chunks.
    
    • Example: 512MB total / 2MB chunks = 256. RAMSIZE = 0x100
      
  • BANKALLOCATION - these bits are used to optimze the bandwidth in and out of the mDDR. Section "BANKALLOCATION Parameter" in the TRM describes the details. To optimize your bandwidth, you need to determine which access pattern you typically use in your application, and set the BANKALLOCATION bits accordingly. This can potentially reduce the overhead of accessing the mDDR, resulting in improved performance.
  • B32NOT16 - 16bit or 32bit bus width
  • DEEPPD - does your memory support deep power down? If so, set this to 1
  • DDRTYPE - always set to 0
  • RAMTYPE - for mDDR set to 0x1

• SDRC_MR_p - Other than the CAS latency field, this register has typical values for all configurations. Choose the CAS latency as defined in your memory datasheet. Typical value for this register is 0x00000032 (CAS latency = 3).

• SDRC_EMR2_p - Typical value for this register is 0x00000000.

AC timing registers

• SDRC_ACTIM_CTRLA_p and SDRC_ACTIM_CTRLB_p

This spreadsheet will help you determine the optimal values for the AC timing registers:

OMAP35x DDR register calc tool

The values in yellow need to be changed based on the datasheet values for your memory. Ensure that you enter the correct values for the speed grade of your device. The tCK value should represent the speed at which you will be running the device (not necessarily the minimum value in the datasheet). The register values for the OMAP35x AC timing registers will be calculated based on these inputs. For more conservative values, you can back off these optimal values (ie, increase each value by 1 or 2).

Setting Refresh rate

• SDRC_RFR_CTRL_p - To set the refresh rate, get the Periodic Refresh interval tREFI from the memory datasheet. Note that this value is typcially in the us range. Some datasheets may refer to a "Refresh Interval time" in the millisecond range (64ms, for example), however, this value needs to be divided by the number of refresh cycles needed (typically 8000).
  
  • ARCV

For 166MHz systems, tCK would be 6ns.

tREFI/tCK - 50 = ARCV

For example:

(7.8us/6ns) - 50 = 1250 -> 0x4E2

Use same value for SDRC_RFR_CTRL_0.ARCV and SDRC_RFR_CTRL_1.ARCV

• • ARE value is typically 0x1 to perform one autorefresh command each time the autorefresh command counts down to 0.

General Registers

For more details on each of these registers, please refer to the OMAP35x TRM.

• SDRC_SYSCONFIG - typical value for normal operation: 0x00000010
  • NOMEMORYMRS - typically set to 0 to allow commands to be sent to the mDDR
  • IDLEMODE - set to 0x2 to enable Smart Idle. All other settings are reserved.
  • SOFTRESET - set to 0 for normal mode.

• SDRC_CS_CFG

This register configures CS1 address space (see TRM for details). There a 2 chip selects (SDRC_CS0 and SDRC_CS1) on OMAP35x. Typically only CS0 is used, but if your application requires more capacity, or if your memory configuration requires the use of 2 chip selects because of loading restrictions, then CS1 would be used. For configurations which use just CS0, this register can be left in its default setting.

• SDRC_SHARING

For 32-bit configurations, the typical value for this register is 0x00000100. This will define a 32-bit data lane for both CS0 and CS1. This setting will work for either CS0 only or CS0/CS1 configurations.
For 16-bit configurations, the typical value for this register is 0x00003700. This will define a 16-bit data lane for both CS0 and CS1. This setting will work for either CS0 only or CS0/CS1 configurations

• SDRC_ERR_TYPE

This register is typically left in its default value.

• SDRC_DLLA_CTRL

Typical value is 0x0000000A

• SDRC_POWER_REG

Typical value is 0x00000081.

More Tips

• OMAP35x can only handle a max of 1GByte of memory on each chip select. Furthermore, it is recommended that you only present 2 loads to the OMAP35x SDRC signals. Some memories increase capacity by stacking dies in their packages. For example, a package with 2 dies presents 2 loads to the SDRC signals. Ensure that your configuration does not present more than 2 loads to the OMAP35x SDRC signals

8Gb = 1GByte
4Gb = 512MByte
2Gb = 256MByte
1Gb = 128MByte