PRU Subsystem Differences Between OMAPL1x8/AM18x and OMAP1x7/AM17x

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This article outlines the PRU subsystem differences between the OMAP-L1x7/C674m (where m is odd)/AM17xx and OMAP-L1x8/C674n (where n is even)/AM18xx devices. Aside from the differences below, all other aspects of the PRU subsystem are the same, including (but not limited to): SOC memory mapping, PRU instruction and data RAM size, SOC interrupt controller mapping, etc.

Constants Table Mapping

The following tables provide the constants table as implemented on OMAP-L1x8/C674n/AM18xx and OMAP-L1x7/C674m/AM17xx devices.

OMAP-L1x8/C674n/AM18xx Specific Constants Table

Entry #	Region Pointed To	Value [31:0]
0	PRU0/1 Local INTC	0x00004000
1	Timer64P0	0x01C20000
2	I2C0	0x01C22000
3	PRU0/1 Local Data	0x00000000
4	PRU1/0 Local Data	0x00002000
5	MMC/SD	0x01C40000
6	SPI0	0x01C41000
7	UART0	0x01C42000
8	McASP0 DMA	0x01D02000
9*	RESERVED	0x01D06000
10*	RESERVED	0x01D0A000
11	UART1	0x01D0C000
12	UART2	0x01D0D000
13	USB0	0x01E00000
14	USB1	0x01E25000
15	UHPI Config	0x01E10000
16*	RESERVED	0x01E12000
17	I2C1	0x01E28000
18	EPWM0	0x01F00000
19	EPWM1	0x01F02000
20*	RESERVED	0x01F04000
21	ECAP0	0x01F06000
22	ECAP1	0x01F07000
23	ECAP2	0x01F08000
24	PRU0/1 Local Data	0x00000n00, n=c24_blk_index[3:0]
25	McASP0 Control	0x01D00n00, n=c25_blk_index[3:0]
26*	RESERVED	0x01D04000
27*	RESERVED	0x01D08000
28	DSP Megamodule RAM/ROM	0x11nnnn00, nnnn=c28_pointer[15:0]
29	EMIFA SDRAM	0x40nnnn00, nnnn=c29_pointer[15:0]
30	Shared RAM	0x80nnnn00, nnnn=c30_pointer[15:0]
31	mDDR/DDR2 Data	0xC0nnnn00, nnnn=c31_pointer[15:0]
* These constants cannot be used due to memory map restrictions. Notes: Constants table entries 24 through 31 are not fully hard-coded, but contain a programmable bitfield (ex. c24_blk_index[3:0]) that is programmable through the PRU control register space (0x01C3_7000 - 0x01C3_73FF for PRU0 and 0x01C3_7800 - 0x01C3_7BFF for PRU1).

OMAP-L1x7/C674m/AM17xx Specific Constants Table

Entry #	Region Pointed To	Value [31:0]
0	PRU0/1 Local INTC	0x00004000
1	Timer64P0	0x01C20000
2	I2C0	0x01C22000
3	PDSP0/1 Local Data	0x00000000
4	PDSP1/0 Local Data	0x00002000
5	MMC/SD	0x01C40000
6	SPI0	0x01C41000
7	UART0	0x01C42000
8	McASP0 DMA	0x01D02000
9	McASP1 DMA	0x01D06000
10	McASP2 DMA	0x01D0A000
11	UART1	0x01D0C000
12	UART2	0x01D0D000
13	USB0	0x01E00000
14	USB1	0x01E25000
15	UHPI Config	0x01E10000
16	SPI1	0x01E12000
17	I2C1	0x01E28000
18	EPWM0	0x01F00000
19	EPWM1	0x01F02000
20	EPWM2	0x01F04000
21	ECAP0	0x01F06000
22	ECAP1	0x01F07000
23	ECAP2	0x01F08000
24	PRU0/1 Local Data	0x00000n00, n=c24_blk_index[3:0]
25	McASP0 Control	0x01D00n00, n=c25_blk_index[3:0]
26	McASP1 Control	0x01D04n00, n=c26_blk_index[3:0]
27	McASP2 Control	0x01D08n00,n=c27_blk_index[3:0]
28	DSP Megamodule RAM/ROM	0x11nnnn00, nnnn=c28_pointer[15:0]
29	EMIFA SDRAM	0x40nnnn00, nnnn=c29_pointer[15:0]
30	Shared RAM	0x80nnnn00, nnnn=c30_pointer[15:0]
31	EMIFB Data	0xC0nnnn00, nnnn=c31_pointer[15:0]
Notes: Constants table entries 24 through 31 are not fully hard-coded, but contain a programmable bitfield (ex. c24_blk_index[3:0]) that is programmable through the PRU control register space (0x01C3_7000 - 0x01C3_73FF for PRU0 and 0x01C3_7800 - 0x01C3_7BFF for PRU1).

System Event Mapping

The following tables provide the PRU subsystem system event assignment as implemented on OMAP-L1x8/C674n/AM18xx and OMAP-L1x7/C674m/AM17xx devices. Note that the OMAP-L1x8/C674n/AM18xx devices have two potential event assignments, depending on the setting of PRUSSEVTSEL. The OMAP-L1x7/C674m/AM17xx devices have a single fixed assignment for the 32 system events.

OMAP-L1x8/C674n/AM18xx Specific PRUSS System Event Assignment

	PRUSSEVTSEL = 0	PRUSSEVTSEL = 1
Event	Description	Description
0	Emulation Suspend Signal (Software Use Only)	Emulation Suspend Signal (Software Use Only)
1	ECAP0 Interrupt	Timer64P2_T12CMPEVT0
2	ECAP1 Interrupt	Timer64P2_T12CMPEVT1
3	Timer64P0 Event Out 12	Timer64P2_T12CMPEVT2
4	ECAP2 Interrupt	Timer64P2_T12CMPEVT3
5	McASP0 TX DMA Request	Timer64P2_T12CMPEVT4
6	McASP0 RX DMA Request	Timer64P2_T12CMPEVT5
7	McBSP0 TX DMA Request	Timer64P2_T12CMPEVT6
8	McBSP0 RX DMA Request	Timer64P2_T12CMPEVT7
9	McBSP1 TX DMA Request	Timer64P3_T12CMPEVT0
10	McBSP1 RX DMA Request	Timer64P3_T12CMPEVT1
11	SPI0 Interrupt 0	Timer64P3_T12CMPEVT2
12	SPI1 Interrupt 0	Timer64P3_T12CMPEVT3
13	UART0 Interrupt	Timer64P3_T12CMPEVT4
14	UART1 Interrupt	Timer64P3_T12CMPEVT5
15	I2C0 Interrupt	Timer64P3_T12CMPEVT6
16	I2C1 Interrupt	Timer64P3_T12CMPEVT7
17	UART2 Interrupt	Timer64P0_T12CMPEVT0 or Timer64P0_T12CMPEVT1 or Timer64P0_T12CMPEVT2 or Timer64P0_T12CMPEVT3 or Timer64P0_T12CMPEVT4 or Timer64P0_T12CMPEVT5 or Timer64P0_T12CMPEVT6 or Timer64P0_T12CMPEVT7
18	MMCSD0 Interrupt 0	Timer64P2 Event Out 12
19	MMCSD0 Interrupt 1	Timer64P3 Event Out 12
20	USB0 (USB2.0 HS OTG) Subsystem Interrupt Request (aggregated from subsystem’s INTD)	Timer64P1 Event Out 12
21	USB1 (USB1.1 FS OHCI) Subsystem IRQ Interrupt	UART1 Interrupt
22	Timer64P0 Event Out 34	UART2 Interrupt
23	ECAP0 input (output from mux)	SPI0 Interrupt 0
24	EPWM0 Interrupt	EPWM0 Interrupt
25	EPWM1 Interrupt	EPWM1 Interrupt
26	SATA Interrupt	SPI1 Interrupt 0
27	EDMA TPCC0 EDMAINT[2] (region 2)	GPIO Bank 0 Interrupt
28	EDMA TPCC0 EDMAINT[3] (region 3)	GPIO Bank 1 Interrupt
29	UHPI CPU_INT	McBSP0 TX DMA Request
30	EPWM0TZ Interrupt or EPWM1TZ Interrupt	McBSP0 RX DMA Request
31	McASP0 TX Interrupt or McASP0 RX Interrupt	McASP0 TX Interrupt or McASP0 RX Interrupt

OMAP-L1x7/C674m/AM17xx Specific PRUSS System Event Assignment

Event	Description	Event	Description
0	Emulation Suspend Signal (Software Use Only)	16	I2C1 Interrupt
1	ECAP0 Interrupt	17	UART2 Interrupt
2	ECAP1 Interrupt	18	MMCSD Interrupt0
3	Timer64P0 Event Out 12	19	MMCSD Interrupt1
4	ECAP2 Interrupt	20	USB0 Subsystem Interrupt Request (Aggregated, from sub-system’s INTD)
5	McASP0 TX DMA Request	21	USB1 Subsystem IRQ Interrupt
6	McASP0 RX DMA Request	22	Timer64P0 Event Out 34
7	McASP1 TX DMA Request	23	eCAP0 Input (output from mux)
8	McASP1 RX DMA Request	24	EPWM0 Interrupt
9	McASP2 TX DMA Request	25	EPWM1 Interrupt
10	McASP2 RX DMA Request	26	EPWM2 Interrupt
11	SPI0 Interrupt0	27	EDMA TPCC EDMAINT[2] (region 2)
12	SPI1 Interrupt0	28	EDMA TPCC EDMAINT[3] (region 3)
13	UART0 Interrupt	29	UHPI CPU_INT
14	UART1 Interrupt	30	EPWM0TZ Interrupt or EPWM1TZ Interrupt or EPWM2TZ Interrupt
15	I2C0 Interrupt	31	McASP0 TX INT or McASP0 RX INT or McASP1 TX INT or McASP1 RX INT or McASP2 TX INT or McASP2 RX INT

Pins

OMAP-L1x7/C674m/AM17xx devices do not support any PRU pins.  OMAP-L1x8/C674n/AM18xx devices do support PRU pins, see the device data sheet for more information.

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