PRU Interrupt Controller

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This article is part of a collection of articles describing the PRU subsystem included in OMAP-L1x8/C674m/AM18xx devices (where m is an even number).  To navigate to the main page for the PRU subsystem click on the link above.

Introduction

The PRUSS interrupt controller (INTC) is an hardware interface between interrupts coming from different parts of the system (these are referred to as system events), and the PRUs interrupt inputs.

The PRUSS INTC has the following features:

• Capturing up to 32 System Events external to the PRUSS.
• 32 additional System events generated by the PRUs.
• Supports up to 10 interrupt channels.
• Generation of 10 Host Interrupts
  • 2 Host Interrupts for the PRUs.
  • 8 Host Interrupts exported from the PRUSS for signaling the host (ARM/DSP) interrupt controllers.
• Each system event can be enabled and disabled.
• Each host event can be enabled and disabled.
• Hardware prioritization of events.

Interrupt Mapping

The PRUSS INTC supports up to 64 system interrupts from different peripherals and PRUs to be mapped to 10 channels inside the INTC (see Figure 1). Interrupts from these 10 channels are further mapped to 10 Host Interrupts.

• Any of the 64 system interrupts can be mapped to any of the 10 channels.
• Multiple interrupts can be mapped to a single channel.
• An interrupt should not be mapped to more than one channel.
• Any of the 10 channels can be mapped to any of the 10 host interrupts. It is recommended to map channel "x" to host interrupt "x", where x is from 0 to 9
• A channel should not be mapped to more than one host interrupt.
• For channels mapping to the same host interrupt, lower number channels have higher priority.
• For interrupts on same channel, priority is determined by the hardware interrupt number. The lower the interrupt number, the higher the priority.
• Host Interrupt 0 is connected to bit 30 in register 31 of PRU0 and PRU1.
• Host Interrupt 1 is connected to bit 31 in register 31 for PRU0 and PRU1.
• Host Interrupts 2 through 9 exported from PRUSS for signaling ARM and DSP interrupt controllers generating system Events PRUSS_EVTOUT0 to PRUSS_EVTOUT7 respectively.

PRUSS System Events

System events 0 through 31 are external to the PRUSS subsystem and generated from different peripherals. The source of the first 32 events from the device is listed in the Table 1.

System events 32 to 63 are generated by a PRU writing to its own R31 register. The system interrupt is used to either post a completion event to one of the host CPUs (ARM/DSP) or to signal the other PRU core of the PRUSS. For more information on the steps to generate the system events 32 to 63 refer to "Event out Mapping (R31): PRU System Events"

The device includes a mux that with a single select signal selects the PRUSS EVT inputs as shown in the table below. The control signal, PRUSSEVTSEL, can be modified by software in system register CFGCHIP3[3]. PRUSSEVTSEL defaults to 0 after reset. Note that not all system events are defined for all devices. Refer to the device datasheet or System Reference Guide for more information.

Table 1: PRUSS System Events [0:31] Assignments

	PRUSSEVTSEL = 0	PRUSSEVTSEL = 1
Event	Description	Description
0	Emulation Suspend Signal (Software Use Only)	Emulation Suspend Signal (Software Use Only)
1	ECAP0 Interrupt	Timer64P2_T12CMPEVT0
2	ECAP1 Interrupt	Timer64P2_T12CMPEVT1
3	Timer64P0 Event Out 12	Timer64P2_T12CMPEVT2
4	ECAP2 Interrupt	Timer64P2_T12CMPEVT3
5	McASP0 TX DMA Request	Timer64P2_T12CMPEVT4
6	McASP0 RX DMA Request	Timer64P2_T12CMPEVT5
7	McBSP0 TX DMA Request	Timer64P2_T12CMPEVT6
8	McBSP0 RX DMA Request	Timer64P2_T12CMPEVT7
9	McBSP1 TX DMA Request	Timer64P3_T12CMPEVT0
10	McBSP1 RX DMA Request	Timer64P3_T12CMPEVT1
11	SPI0 Interrupt 0	Timer64P3_T12CMPEVT2
12	SPI1 Interrupt 0	Timer64P3_T12CMPEVT3
13	UART0 Interrupt	Timer64P3_T12CMPEVT4
14	UART1 Interrupt	Timer64P3_T12CMPEVT5
15	I2C0 Interrupt	Timer64P3_T12CMPEVT6
16	I2C1 Interrupt	Timer64P3_T12CMPEVT7
17	UART2 Interrupt	Timer64P0_T12CMPEVT0 or Timer64P0_T12CMPEVT1 or Timer64P0_T12CMPEVT2 or Timer64P0_T12CMPEVT3 or Timer64P0_T12CMPEVT4 or Timer64P0_T12CMPEVT5 or Timer64P0_T12CMPEVT6 or Timer64P0_T12CMPEVT7
18	MMCSD0 Interrupt 0	Timer64P2 Event Out 12
19	MMCSD0 Interrupt 1	Timer64P3 Event Out 12
20	USB0 (USB2.0 HS OTG) Subsystem Interrupt Request (aggregated from subsystem’s INTD)	Timer64P1 Event Out 12
21	USB1 (USB1.1 FS OHCI) Subsystem IRQ Interrupt	UART1 Interrupt
22	Timer64P0 Event Out 34	UART2 Interrupt
23	ECAP0 input (output from mux)	SPI0 Interrupt 0
24	EPWM0 Interrupt	EPWM0 Interrupt
25	EPWM1 Interrupt	EPWM1 Interrupt
26	SATA Interrupt	SPI1 Interrupt 0
27	EDMA3_0_CC0_INT2 (region 2)	GPIO Bank 0 Interrupt
28	EDMA3_0_CC0_INT3 (region 3)	GPIO Bank 1 Interrupt
29	UHPI CPU_INT	McBSP0 TX DMA Request
30	EPWM0TZ Interrupt or EPWM1TZ Interrupt	McBSP0 RX DMA Request
31	McASP0 TX Interrupt or McASP0 RX Interrupt	McASP0 TX Interrupt or McASP0 RX Interrupt

ARM and DSP Interrupt Controller Mapping

Events PRUSS_EVTOUT0 to PRUSS_EVTOUT7 are mapped to the ARM and DSP interrupt controllers. The following tables show the interrupt mapping.

Table 2: ARM Interrupt Controller Mapping

Event Number	Source
3	EVTOUT0
4	EVTOUT1
5	EVTOUT2
6	EVTOUT3
7	EVTOUT4
8	EVTOUT5
9	EVTOUT6
10	EVTOUT7

Table 3: DSP Interrupt Controller Mapping

Event Number	Source
6	EVTOUT0
17	EVTOUT1
22	EVTOUT2
35	EVTOUT3
66	EVTOUT4
39	EVTOUT5
44	EVTOUT6
50	EVTOUT7

INTC Methodology

The INTC module controls the system event mapping to the host interrupt interface. System events are generated by the device peripherals or PRUs. The INTC receives the system interrupts and maps them to internal channels. The channels are used to group interrupts together and to prioritize them. These channels are then mapped onto the host interrupts. Interrupts from system side are active high in polarity. Also, they are pulse type of interrupts.

The INTC encompasses many functions to process the system interrupts and prepare them for the host interface. These functions are: processing, enabling, status, channel mapping, host interrupt mapping, prioritization, and host interfacing. Figure 2 illustrates the flow of system interrupts through the functions to the host. The following subsections describe each part of the flow.

Interrupt Processing

This block does following tasks:

• Synchronization of slower and asynchronous interrupts
• Conversion of polarity to active high
• Conversion of interrupt type to pulse interrupts

After the "processing block", all interrupts will be active high pulses.

Interrupt Enabling

The next stage of INTC is to enable system interrupts based on programmed settings. The following sequence is to be followed to enable interrupts:

1. Enable all host interrupts: By setting the ENABLE bit in the global enable register (GER) to 1, all host interrupts will be enabled. Individual host interrupts are still enabled or disabled from their individual enables and are not overridden by the global enable.
2. Enable required host interrupts: By writing to the INDEX field in the host interrupt enable indexed set register (HIEISR), enable the required host interrupts. The host interrupt to enable is the index value written. This enables the host interrupt output or triggers the output again if that host interrupt is already enabled.
3. Enable required system interrupts: System interrupts that are required to get propagated to host are to be enabled individually by writing to INDEX field in the system interrupt enable indexed set register (EISR). The interrupt to enable is the index value written. This sets the Enable Register bit of the given index.

System interrupts can also be enabled by setting the bits of the system interrupt enable set registers (ESR1-ESR3). Only enabled system interrupts will generate an interrupt to the host.

Interrupt Status Checking

The next stage is to capture which system interrupts are pending. There are two kinds of pending status: raw status and enabled status. Raw status is the pending status of the system interrupt without regards to the enable bit for the system interrupt. The raw status of system interrupts is captured in system interrupt status raw/set registers (SRSR1-SRSR2). Enabled status is the pending status of the system interrupts with the enable bits set. When the enable bit is not set, the enabled status will always be inactive. The enabled status of system interrupts is captured in system interrupt status enabled/clear registers (SECR1-SECR2).

Status of system interrupt ’N’ is indicated by the Nth bit of SECR1-SECR2. Since there are 64 system interrupts, two 32-bit registers are used to capture the enabled status of interrupts. The pending status reflects whether the system interrupt occurred since the last time the status register bit was cleared. Each bit in the status register can be individually cleared.

Interrupt Channel Mapping

The INTC has 10 internal channels to which enabled system interrupts can be mapped. Channel 0 has highest priority and channel 9 has the lowest priority. Channels are used to group the system interrupts into a smaller number of priorities that can be given to a host interface with a very small number of interrupt inputs.

When multiple system interrupts are mapped to the same channel their interrupts are ORed together so that when either is active the output is active. The channel map registers (CMR1-CMR16) define the channel for each system interrupt. There is one register per 4 system interrupts; therefore, there are 16 channel map registers for a system of 64 interrupts. Channels for each system interrupt can be set using these registers.

Host Interrupt mapping

The INTC generates 10 host interrupts which can be .  The hosts can be the two PRUs, the ARM CPU, and DSP CPU.  The 10 channels from the INTC can be mapped to any of the 10 host interrupts. The host map registers (HMR1-HMR3) define the host interrupt for each channel. There is one register per 4 channels; therefore, there are 3 host map registers for 10 channels. Multiple channels can be mapped to the same host interrupt.  When multiple channels are mapped to the same host interrupt prioritization is done to select which interrupt is in the highest-priority channel and which should be sent first to the host.

Interrupt Prioritization

The next stage of the INTC is prioritization. Since multiple interrupts can feed into a single channel and multiple channels can feed into a single host interrupt, it is necessary to read the status of all system interrupts to determine the highest priority interrupt that is pending. The INTC provides hardware to perform this prioritization with a given scheme so that software does not have to do this. There are two levels of prioritization:

• The first level of prioritization is between the active channels for a host interrupt. Channel 0 has the highest priority and channel 9 has the lowest. So the first level of prioritization picks the lowest numbered active channel.
• The second level of prioritization is between the active system interrupts for the prioritized channel. The system interrupt in position 0 has the highest priority and system interrupt 63 has the lowest priority. So the second level of prioritization picks the lowest position active system interrupt.

The highest priority interrupt pending across all host interrupts is stored in the global prioritized index register (GPIR). The highest priority pending interrupt with respect to each host interrupt can be obtained using the host interrupt prioritized index registers (HIPIRn).

Interrupt Nesting

The INTC can also perform a nesting function in its prioritization. Nesting is a method of disabling certain interrupts (usually lower-priority interrupts) when an interrupt is taken so that only those desired interrupts can trigger to the host while it is servicing the current interrupt. The typical usage is to nest on the current interrupt and disable all interrupts of the same or lower priority (or channel). Then the host will only be interrupted from a higher priority interrupt.

The nesting is done in 1 of 3 methods:

• Nesting for all host interrupts, based on channel priority: When an interrupt is taken, the nesting level is set to its channel priority. From then, that channel priority and all lower priority channels will be disabled from generating host interrupts and only higher priority channels are allowed. When the interrupt is completely serviced, the nesting level is returned to its original value. When there is no interrupt being serviced, there are no channels disabled due to nesting. The global nesting level register (GNLR) allows the checking and setting of the global nesting level across all host interrupts. The nesting level is the channel (and all of lower priority channels) that are nested out because of a current interrupt.

• Nesting for individual host interrupts, based on channel priority: Always nest based on channel priority for each host interrupt individually. When an interrupt is taken on a host interrupt, then, the nesting level is set to its channel priority for just that host interrupt, and other host interrupts do not have their nesting affected. Then for that host interrupt, equal or lower priority channels will not interrupt the host but may on other host interrupts if programmed. When the interrupt is completely serviced the nesting level for the host interrupt is returned to its original value. The host interrupt nesting level registers (HINLR1 and HINLR2) display and control the nesting level for each host interrupt. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt.

• Software manually performs the nesting of interrupts. When an interrupt is taken, the software will disable all the host interrupts, manually update the enables for any or all the system interrupts, and then re-enables all the host interrupts. This now allows only the system interrupts that are still enabled to trigger to the host. When the interrupt is completely serviced the software must reverse the changes to re-enable the nested out system interrupts. This method requires the most software interaction but gives the most flexibility if simple channel based nesting mechanisms are not adequate.

Interrupt Status Clearing

After servicing the interrupt (after execution of the ISR), interrupt status is to be cleared. If a system interrupt status is not cleared, then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly.It is also essential to clear all system interrupts before the PRU is halted as the PRU does not power down unless all the interrupt status are cleared. For clearing the status of an interrupt, whose interrupt number is N, write a 1 to the Nth bit position in the system interrupt status enabled/clear registers (SECR1-SECR2). System interrupt N can also be cleared by writing the value N into the system interrupt status indexed clear register (SICR).

Interrupt Disabling

At any time, if any interrupt is not to be propagated to the host, then that interrupt should be disabled. For disabling an interrupt whose interrupt number is N, write a 1 to the Nth bit in the system interrupt enable clear registers (ECR1-ECR2). System interrupt N can also be disabled by writing the value N in the system interrupt enable indexed clear register (EICR).

Configuring the Interrupt Controller

Follow these steps to configure the interrupt controller.

1. Set polarity and type of system event through the System Interrupt Polarity Registers (SIPR1 and SPIR2) and the System Interrupt Type Registers (SITR1 and SITR2).  Polarity of all system interrupts is always high.  Type of all system interrupts is always pulse.
2. Map system event to INTC channel through CHANMAP registers.
3. Map channel to host interrupt through HOSTMAP registers.  Recommend channel “x” be mapped to host interrupt “x”.
4. Clear system interrupt by writing 1s to SECR registers.
5. Enable host interrupt by writing index value to HOSTINTENIDX register.
6. Enable interrupt nesting if desired.
7. Globally enable all interrupts through GLBLEN register.

INTC Registers

Table 4 lists the memory-mapped registers for the INTC. See the PRUSS memory map for the memory address of these registers.

Table 4: PRUSS Interrupt Controller (INTC) Registers

Address Offset	Register Name	Description
0x000	REVID	Revision ID Register
0x004	CONTROL	Control Register
0x010	GLBLEN	Global Enable Register
0x01C	GLBLNSTLVL	Global Nesting Level Register
0x020	STATIDXSET	System Interrupt Status Indexed Set Register
0x024	STATIDXCLR	System Interrupt Status Indexed Clear Register
0x028	ENIDXSET	System Interrupt Enable Indexed Set Register
0x02C	ENIDXCLR	System Interrupt Enable Indexed Clear Register
0x034	HSTINTENIDXSET	Host Interrupt Enable Indexed Set Register
0x038	HSTINTENIDXCLR	Host Interrupt Enable Indexed Clear Register
0x080	GLBLPRIIDX	Global Prioritized Index Register
0x200	STATSETINT0	System Interrupt Status Raw/Set Register 0
0x204	STATSETINT1	System Interrupt Status Raw/Set Register 1
0x280	STATCLRINT0	System Interrupt Status Enabled/Clear Register 0
0x284	STATCLRINT1	System Interrupt Status Enabled/Clear Register 1
0x300	ENABLESET0	System Interrupt Enable Set Register 0
0x304	ENABLESET1	System Interrupt Enable Set Register 1
0x380	ENABLECLR0	System Interrupt Enable Clear Register 0
0x384	ENABLECLR1	System Interrupt Enable Clear Register 1
0x400 – 0x440	CHANMAP0-CHANMAP15	Channel Map Registers 0-15
0x800-0x808	HOSTMAP0-HOSTMAP2	Host Map Register 0-2
0x900 – 0x928	HOSTINTPRIIDX0-HOSTINTPRIIDX9	Host Interrupt Prioritized Index Registers 0-9
0xD00	POLARITY0	System Interrupt Polarity Register 0
0xD04	POLARITY1	System Interrupt Polarity Register 1
0xD80	TYPE0	System Interrupt Type Register 0
0xD84	TYPE1	System Interrupt Type Register 1
0x1100 – 0x1128	HOSTINTNSTLVL0-HOSTINTNSTLVL9	Host Interrupt Nesting Level Registers 0-9
0x1500	HOSTINTEN	Host Interrupt Enable Register

Revision Register (REVID)

The Revision Register contains the ID and revision information.

Bits	Field	Type	Reset	Description
31:0	REV	r/o	1	Revision ID

Control Register (CONTROL)

The Control Register holds global control parameters and can forces a soft reset on the module.

Bits	Field	Type	Reset	Description
31:4	reserved	r/o	0	Always read as 0. Writes have no effect.
3:2	NESTMODE	r/w	0	The nesting mode. 0 = no nesting 1 = automatic individual nesting (per host interrupt) 2 = automatic global nesting (over all host interrupts) 3 = manual nesting
1:0	reserved	r/o	0	Always read as 0. Writes have no effect.

Global Enable Register (GLBLEN)

The Global Enable Register enables all the host interrupts. Individual host interrupts are still enabled or disabled from their individual enables and are not overridden by the global enable.

Bits	Field	Type	Reset	Description
31:1	reserved	r/o	0	Always read as 0. Writes have no effect.
0	ENABLE	r/w	0	The current global enable value when read. Writes set the global enable

Global Nesting Level Register (GLBLNSTLVL)

The Global Nesting Level Register allows the checking and setting of the global nesting level across all host interrupts when automatic global nesting mode is set. The nesting level is the channel (and all of lower priority) that are nested out because of a current interrupt. This register is only available when nesting is configured.

Bits	Field	Type	Reset	Description
31	OVERRIDE	w/o	0	Always read as 0. Writes of 1 override the automatic nesting and set the nesting_level to the written data.
30:9	reserved	r/o	0	Always read as 0. Writes have no effect.
8:0	NESTLEVEL	r/w	0xA	The current global nesting level (highest channel that is nested). Writes set the nesting level. In auto nesting mode this value is updated internally unless the auto_override bit is set.

System Interrupt Status Indexed Set Register (STATIDXSET)

The System Interrupt Status Indexed Set Register allows setting the status of an interrupt. The interrupt to set is the index value written. This sets the Raw Status Register bit of the given index.

Bits	Field	Type	Reset	Description
31:10	reserved	r/o	0	Always read as 0. Writes have no effect.
9:0	INDEX	w/s	0	Writes set the status of the interrupt given in the index value. Reads return 0.

System Interrupt Status Indexed Clear Register (STATIDXCLR)

The System Interrupt Status Indexed Clear Register allows clearing the status of an interrupt. The interrupt to clear is the index value written. This clears the Raw Status Register bit of the given index.

Bits	Field	Type	Reset	Description
31:10	reserved	r/o	0	Always read as 0. Writes have no effect.
9:0	INDEX	w/c	0	Writes clear the status of the interrupt given in the index value. Reads return 0.

System Interrupt Enable Indexed Set Register (ENIDXSET)

The System Interrupt Enable Indexed Set Register allows enabling an interrupt. The interrupt to enable is the index value written. This sets the Enable Register bit of the given index.

Bits	Field	Type	Reset	Description
31:10	reserved	r/o	0	Always read as 0. Writes have no effect.
9:0	INDEX	w/s	0	Writes set the enable of the interrupt given in the index value. Reads return 0.

System Interrupt Enable Indexed Clear Register (ENIDXCLR)

The System Interrupt Enable Indexed Clear Register allows disabling an interrupt. The interrupt to disable is the index value written. This clears the Enable Register bit of the given index.

Bits	Field	Type	Reset	Description
31:10	reserved	r/o	0	Always read as 0. Writes have no effect.
9:0	INDEX	w/c	0	Writes clear the enable of the interrupt given in the index value. Reads return 0.

Host Interrupt Enable Indexed Set Register (HOSTINTENIDX)

The Host Interrupt Enable Indexed Set Register allows enabling a host interrupt output. The host interrupt to enable is the index value written. This enables the host interrupt output or triggers the output again if already enabled.

Bits	Field	Type	Reset	Description
31:10	reserved	r/o	0	Always read as 0. Writes have no effect.
9:0	INDEX	w/s	0	Writes set the enable of the host interrupt given in the index value. Reads return 0.

Host Interrupt Enable Indexed Clear Register (HIDISR)

The Host Interrupt Enable Indexed Clear Register allows disabling a host interrupt output. The host interrupt to disable is the index value written. This disables the host interrupt output.

Bits	Field	Type	Reset	Description
31:10	reserved	r/o	0	Always read as 0. Writes have no effect.
9:0	index	w/c	0	Writes clear the enable of the host interrupt given in the index value. Reads return 0.

Global Prioritized Index Register (GPIR)

The Global Prioritized Index Register shows the interrupt number of the highest priority interrupt pending across all the host interrupts.

Bits	Field	Type	Reset	Description
31	none	r/o	1	No Interrupt is pending. Can be used by host to test for a negative value to see if no interrupts are pending.
30:10	reserved	r/o	0	Always read as 0. Writes have no effect.
9:0	pri_index	r/o	0	The currently highest priority interrupt index pending across all the host interrupts.

System Interrupt Status Raw/Set Register 1 (SRSR1)

The System Interrupt Status Raw/Set Registers show the pending enabled status of the system interrupts. Software can write to the Status Set Registers to manually set a system interrupt. There is one bit per system interrupt.

Bits	Field	Type	Reset	Description
31:0	raw_status	w/s	0	System interrupt raw status and setting of the system interrupts 0 to 31. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect.

System Interrupt Status Raw/Set Register 2 (SRSR2)

The System Interrupt Status Raw/Set Registers show the pending enabled status of the system interrupts. Software can write to the Status Set Registers to manually set a system interrupt. There is one bit per system interrupt.

Bits	Field	Type	Reset	Description
31:0	raw_status	w/s	0	System interrupt raw status and setting of the system interrupts 32 to 63. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect.

System Interrupt Status Enabled/Clear Register 1 (SECR1)

The System Interrupt Status Enabled/Clear Registers show the pending enabled status of the system interrupts. Software can write to the Status Clear Registers to clear a system interrupt after it has been serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. There is one bit per system interrupt.

Bits	Field	Type	Reset	Description
31:0	enabled_status	w/c	0	System interrupt enabled status and clearing of the system interrupts 0 to 31. Reads return the enabled status (before enabling with the Enable Registers). Write a 1 in a bit position to clear the status of the system interrupt. Writing a 0 has no effect.

System Interrupt Status Enabled/Clear Register 2 (SECR2)

The System Interrupt Status Enabled/Clear Registers show the pending enabled status of the system interrupts. Software can write to the Status Clear Registers to clear a system interrupt after it has been serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. There is one bit per system interrupt.

Bits	Field	Type	Reset	Description
31:0	enabled_status	w/c	0	System interrupt enabled status and clearing of the system interrupts 32to 63. Reads return the enabled status (before enabling with the Enable Registers). Write a 1 in a bit position to clear the status of the system interrupt. Writing a 0 has no effect.

System Interrupt Enable Set Register 1(ESR1)

The System Interrupt Enable Set Register enables system interrupts to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt.

Bits	Field	Type	Reset	Description
31:0	enable	w/s	0	System interrupt enables system interrupts 0 to 31. Read returns the enable value (0 = disabled, 1 = enabled) Write a 1 in a bit position to set that enable. Writing a 0 has no effect.

System Interrupt Enable Set Register 2(ESR2)

The System Interrupt Enable Set Register enables system interrupts to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt.

Bits	Field	Type	Reset	Description
31:0	enable	w/s	0	System interrupt enables system interrupts 32 to 63. Read returns the enable value (0 = disabled, 1 = enabled) Write a 1 in a bit position to set that enable. Writing a 0 has no effect.

System Interrupt Enable Clear Register 1 (ECR1)

The System Interrupt Enable Clear Register disables system interrupts to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt. .

Bits	Field	Type	Reset	Description
31:0	enable	w/c	0	System interrupt enables system interrupts 0 to 31. Read returns the enable value (0 = disabled, 1 = enabled) Write a 1 in a bit position to clear that enable. Writing a 0 has no effect.

System Interrupt Enable Clear Register 2 (ECR2)

The System Interrupt Enable Clear Register disables system interrupts to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt.

Bits	Field	Type	Reset	Description
31:0	enable	w/c	0	System interrupt enables system interrupts 32 to 63. Read returns the enable value (0 = disabled, 1 = enabled) Write a 1 in a bit position to clear that enable. Writing a 0 has no effect.

Channel Map Registers (CMR1-CMR16)

The Channel Map Registers specify the channel for each system interrupt. There is one register per 4 system interrupts.

Bits	Field	Type	Reset	Description
31:24	SysN3_map	r/w	0	Sets the channel for the system interrupt N + 3.
23:16	SysN2_map	r/w	0	Sets the channel for the system interrupt N + 2.
15:8	SysN1_map	r/w	0	Sets the channel for the system interrupt N + 1.
7:0	SysN_map	r/w	0	Sets the channel for the system interrupt N.

Host Interrupt Map Registers (HMR1-HMR3)

The Host Interrupt Map Registers define the host interrupt for each channel. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only.

Bits	Field	Type	Reset	Description
31:24	ChanN3_map	r/w	0	Sets the host interrupt for channel N + 3
23:16	ChanN2_map	r/w	0	Sets the host interrupt for channel N + 2
15:8	ChanN1_map	r/w	0	Sets the host interrupt for channel N + 1
7:0	ChanN_map	r/w	0	Sets the host interrupt for channel N

Host Interrupt Prioritized Index Registers (HIPIR1-HIPIR10)

The Host Interrupt Prioritized Index Registers show the highest priority current pending interrupt for the host interrupt. There is one register per host interrupt.

Bits	Field	Type	Reset	Description
31	none	r/o	1	No pending interrupt.
30:10	reserved	r/o	0	Reads return 0. Writes has no effect.
9:0	pri_index	r/o	0	Interrupt number of the highest priority pending interrupt for this host interrupt.

System Interrupt Polarity Register 1 (SIPR1)

The System Interrupt Polarity Registers define the polarity of the system interrupts. The polarity of all system interrupts is active high; always write 1 to the bits of this register.

Bits	Field	Type	Reset	Description
31:0	polarity	r/w	Default_polarity[N]	Interrupt polarity of the system interrupts 0 to 31. 0 = active low 1 = active high

System Interrupt Polarity Register 2 (SIPR2)

The System Interrupt Polarity Registers define the polarity of the system interrupts. The polarity of all system interrupts is active high; always write 1 to the bits of this register.

Bits	Field	Type	Reset	Description
31:0	polarity	r/w	Default_polarity[N]	Interrupt polarity of the system interrupts 32 to 63. 0 = active low 1 = active high

System Interrupt Type Register 1 (SITR1)

The Interrupt Type Registers define the type of the system interrupts. The type of all system interrupts is pulse; always write 0 to the bits of this register.

Bits	Field	Type	Reset	Description
31:0	type	r/w	Default_type[N]	Interrupt type of the system interrupts 0 to 31. 0 = level or pulse interrupt 1 = edge interrupt (required edge detect)

System Interrupt Type Register 2 (SITR2)

The Interrupt Type Registers define the type of the system interrupts. The type of all system interrupts is pulse; always write 0 to the bits of this register.

Bits	Field	Type	Reset	Description
31:0	type	r/w	Default_type[N]	Interrupt type of the system interrupts 32 to 63. 0 = level or pulse interrupt 1 = edge interrupt (required edge detect)

Host Interrupt Nesting Level Registers (HINLR1-HINLR10)

The Host Interrupt Nesting Level Registers display and control the nesting level for each host interrupt. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt.

Bits	Field	Type	Reset	Description
31	auto_override	w/o	0	Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data.
30:9	reserved	r/o	0	Reads return 0. Writes has no effect.
8:0	nesting_level	r/w	0	Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used.

Host Interrupt Enable Registers (HIER)

The Host Interrupt Enable Registers enable or disable individual host interrupts. These work separately from the global enables. There is one bit per host interrupt. These bits are updated when writing to the Host Interrupt Enable Index Set and Host Interrupt Enable Index Clear registers.

Bits	Field	Type	Reset	Description
31:10	reserved	r/o	0	Reads return 0. Writes has no effect.
9:0	enables	r/w	0	The enable of the host interrupts (one per bit). 0 = disabled 1 = enabled

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