NOTICE: The Processors Wiki will End-of-Life on January 15, 2021. It is recommended to download any files or other content you may need that are hosted on processors.wiki.ti.com. The site is now set to read only.

PDK/PDK TDA PM User Guide

From Texas Instruments Wiki
Jump to: navigation, search
Pdk tda home page.png

Introduction[edit]

Power Management (PM) in Advanced Driver Assist Systems (ADAS) requires setting the right power and clock configurations which allow any IP to consume optimal power. This helps not only reduce the total power consumed by the device but also manage thermal dissipation of the silicon. This document looks at the aspects of power management framework developed for the TDAx family of devices. The following diagram gives the top level view of the power management software stack. Essentially the software stack is divided into two layers PMHAL and PMLIB.

PM Software components.png


The power management (PM) software enables optimal power consumption and thermal management scalable across TDA devices. It is divided into three layers namely:

  • PRCM Database (DB): abstracts the SoC specific PRCM details regarding the registers, the partitioning of the device and the clock tree details.
  • Power Manager Hardware Abstraction Layer (PMHAL): abstracts the programming sequence of atomic power management actions like configuring a PD, CD, PLL, bandgap thermal sensors etc.
  • Application Interface Layer (PM Library - PMLIB): abstracts all PRCM architecture details to the application where the developer provides top-level requests of switching on or off a module or configuring a certain module clock to a certain desired frequency and putting CPUs to low power.

The PM Framework’s interaction with other software in the system is as shown in the figure below:

PM Framework.png


The PM Framework is available on the all the different cores of the system.

  • A possible configuration and distribution of PM responsibility across cores by a software developer is as given in the figure below. This is not a restrictive division but an example based on the nature of responsibilities of different cores in the Vision SDK Framework.
PM software division.png

Examples[edit]

MPU Retention, DSP, IPU, EVE CPU Idle and Wakeup Test[edit]

This example is available at "<install_path>/packages/ti/drv/pm/examples/cpuidle" for MPU, IPU, DSP and "<install_path>/packages/ti/drv/pm/examples/arp32_cpuidle" for EVE core.
The MPU Retention and wakeup test is an example running on A15 core for tda2xx/tda2ex/tda2px. The DSP, IPU and EVE CPU Idle tests run on their respective cores. This example demonstrates the ability to take the MPU/IPU/DSP/EVE to low power retention mode and then wakeup using a timer interrupt. The example loops through the low power state and wakeup cycle 10 times before declaring success. The example illustrates the use of Power Management HAL and Library APIs which allow the MPU to go to retention and IPU/DSP/EVE to clock gated state.

Running the example[edit]

To run the MPU Retention and Wakeup test, please follow the steps below.

  1. Open CCS & launch the target configuration.
  2. Change the SYSBOOT Switch to debug mode or SD mode if booting from SD card.
  3. Load the “pm_cpuidle_app_a15_0_release.xa15fg” on A15 or “pm_cpuidle_app_c66x_release.xe66” on DSP, “pm_cpuidle_app_ipu1_0_release.xem4” on M4 core present in “<install_path>\packages\ti\binary\pm_cpuidle_app\bin\<PLATFORM>” and execute it from CCS.
Note:
1. For pm_arp32_cpuidle_test_app on Tda2xx/tda2px/Tda3xx, Before connecting the EVM to CCS through JTag, modify the gel files and then 
   reload these gel files as stated below.
   a. For Tda2xx, Enable the macro EVE_SW_CONFIG in TDA2xx_multicore_reset.gel
   b. For Tda3xx, do EVE MMU config for DRM registers after OCMC MMU config in TDA3xx_multicore_reset.gel as defined below.
   c. SetupEveMmuEntry(cpu_num, mmu_num, 14, 0x54160000, 0x54160000, EVE_MMU_PAGESIZE_16M);
2. For Tda2xx/tda2px, before running the test on EVE, run A15 in order to avoid 32 counter in halt state .

On successful execution the following output can be seen on the UART Console.

Clock Rate Configuration Test[edit]

This example is available at "<install_path>/packages/ti/drv/pm/examples/clkrate_manager" The Clock Rate Configuration test is an example running on A15 core and IPU (M4) Core for tda2xx/tda2ex/tda2px and IPU (M4) core for tda3xx. This example demonstrates the ability to read the clock rate for different clocks for a given CPU (MPU/IPU/DSP/GPU/IVA/EVE). The example first reads the current clock configuration and then checks for OPP_NOM, OPP_OD and OPP_HIGH frequencies along with voltage changes by using the PMLIB clock rate APIs before declaring pass or fail. The example illustrates the use of Power Management LIB which allows changing the CPU OPP.

Running the example[edit]

To run the example, please follow the steps below.

  1. Open CCS & launch the target configuration.
  2. Change the SYSBOOT Switch to debug mode or SD mode if booting from SD card.
  3. Load the “pm_clkrate_app_a15_0_release.xa15fg” on A15 core for TDA2xx or “pm_clkrate_app_ipu1_0_release.xem4” on M4 core for TDA3xx/TDA2xx present in “<install_path>\packages\ti\binary\pm_clkrate_app\bin\tda2xx” or “<install_path>\packages\ti\binary\ pm_clkrate_app\bin\tda3xx” and execute it from CCS.

On successful execution the following output can be seen on the UART Console for TDA2xx or CCS Console for TDA3xx

PM System Configuration Test[edit]

This example is available at "<install_path>/packages/ti/drv/pm/examples/systemconfig" The PM System Configuration test is an example running on tda2xx A15 core, tda2xx M4 core and tda3xx IPU (M4) core. This example demonstrates the ability to configure the desired power state for a given module based on the entries in the power spread sheet. The example loops through the different modules and power states and tries to program the same for each module using PM LIB sysconfig APIs before declaring pass or fail. The example illustrates the use of Power Management LIB which allows system configuration.

Running the example[edit]

To run the PM System Configuration test, please follow the steps below

  1. Open CCS & launch the target configuration.
  2. Change the SYSBOOT Switch to debug mode or SD mode if booting from SD card.
  3. Load the “pm_systemconfig_app_a15_0_release.xa15fg” on A15 core for TDA2xx/tda2ex/tda2px or “pm_systemconfig_app_ipu1_0_release.xem4” on M4 core for TDA3xx present in “<install_path>\packages\ti\binary\pm_systemconfig_app\bin\<board>” and execute it from CCS.

On successful execution the following output can be seen on the UART Console for TDA2xx or CCS Console for TDA3xx.

INA based power measurement[edit]

This example is available at "<install_path>/packages/ti/drv/pm/examples/ina226_power_measure" The Junction Temperature Sensor test is an example running on tda2xx A15 core. This example demonstrates the ability to read the power from on board INA226 power monitors. The example loops over the different voltage rails supported by the device and reports the current and power consumed by the device voltage rails. On the TDA2xx board, make the following changes to the TI EVM for the test to pass

  • STEP 1: Change the select for RU113 multiplexer on the board by making R264 = 10k & R265 = NO-POP. This allows DCAN2 Signaling.
  • STEP 2: Then perform a blue wiring for the following connections:
    • DCAN2_TX (JP3 pin 1) to PM_I2C_SDA (J8 pin 2)
    • DCAN2_RX (JP3 pin 2) to PM_I2C_SCL (J8 pin 1)
  • From Software Configure the PAD configuration registers such that the gpio6_14 and gpio6_15 pads operate as I2C3_SDA and I2C3_SCL respectively. Note that this is taken care from software. Additionally ensure SEL_I2C3_CAN2 is high.
Ina266 pm.png

Running the example[edit]

To run the INA 226 power measurement test, please follow the steps below

  1. Open CCS & launch the target configuration.
  2. Change the SYSBOOT Switch to debug mode or SD mode if booting from SD card.
  3. Load the “pm_ina226_app_a15_0_release.xa15fg” on A15 core for TDA2xx present in “<install_path>\packages\ti\binary\pm_ina226_app\bin\tda2xx” and execute it from CCS.

Please see the example log from the console for the INA 226 power measurement test on TDA2xx. The power as measured on your sample can show some varying results depending on the type of sample what is running on the device. Ina266 logs.png

CPU Core Loading[edit]

This example showcases the CORE Loading Software.

The Cores supported are: 

A15_0 			- Dhrystone 80% Load, 20% A15 subsystem in retention, A15_1 is force off mode
IPU1_0 (Cortex M4)	- Dhrystone 80% Load, 20% M4 in WFI.
IPU1_1 (Cortex M4)	- Dhrystone 80% Load, 20% M4 in WFI.
IPU2_0 (Cortex M4)	- Dhrystone 80% Load, 20% M4 in WFI.
IPU2_1 (Cortex M4)	- Dhrystone 80% Load, 20% M4 in WFI.
DSP1   (C66x DSP )	- Maximum Power 80% Load, 20% DSP in AutoClock gate. DSP EDMA programmed to perform L2RAM to L2RAM transfers while Max power test is running on DSP.
DSP2   (C66x DSP )	- Maximum Power 80% Load, 20% DSP in AutoClock gate. DSP EDMA programmed to perform L2RAM to L2RAM transfers while Max power test is running on DSP.
EVE1   (EVE      )	- FFT Power 80% Load, 20% EVE in AutoClock gate. EVE EDMA programmed to perform DDR to DDR transfers while FFT processing is running.

Code for all cores runs from DDR.

GEL Configuration required is:(TDAxxx_multicore_reset.gel) 

#define VISION_SDK_CONFIG      1 /* Applicable for Vision SDK users only */
#define VISION_SDK_CONFIG_OLD  0 /* For VSDK 2.8, set this to 1.
                                 * VISION_SDK_CONFIG should also be set to 1
                                 */
#define EVE_SW_CONFIG          0 /* Applicable for EVE_SW users only
                                 * Effective only when
                                 * VISION_SDK_CONFIG == 0
                                 */

How to run (A15):

  1. . Switch on the board.
  2. . Connect to A15_0.
  3. . Perform CPU reset for A15_0.
  4. . Load the A15 code pm_core_loading_app_a15_0_release.xa15fg
  5. . Code will reach main. If the code runs automatically after loading, make sure you perform A15 CPU reset.
  6. . Run the code on A15_0.
  7. . Logs will start getting printed on UART (every ~3 seconds the code will print on UART console the load)
[A15-0  ]Load Kernel Time Taken = 208

782531: LOAD: CPU: 81%, HWI: 0%, SWI:0%
782535: LOAD: TSK: CORE LOADING: 80%

[A15-0  ]Load Kernel Time Taken = 208

786326: LOAD: CPU: 81%, HWI: 0%, SWI:0%
786330: LOAD: TSK: CORE LOADING: 79%

UART Configuration is: 

Baud Rate: 115200
Data	 : 8 bit
Parity	 : none
Stop	 : 1 bit
Flow Control : none

How to run other cores:

  1. . Connect to A15_0.
  2. . Run the GEL script to enable the respective core in TDA2Px_multicore_reset.gel
  3. . Connect to the desired CPU core.
  4. . Perform CPU Reset.
  5. . Load code for the respective core.
  6. . Code would reach main.
  7. . Make sure A15 is running even if no code is loaded on A15 CPU Core.
  8. . Run the code on the individual cores.

Again each core would send its own message on the UART console.

E2e.jpg {{
  1. switchcategory:MultiCore=
  • For technical support on MultiCore devices, please post your questions in the C6000 MultiCore Forum
  • For questions related to the BIOS MultiCore SDK (MCSDK), please use the BIOS Forum

Please post only comments related to the article PDK/PDK TDA PM User Guide here.

Keystone=
  • For technical support on MultiCore devices, please post your questions in the C6000 MultiCore Forum
  • For questions related to the BIOS MultiCore SDK (MCSDK), please use the BIOS Forum

Please post only comments related to the article PDK/PDK TDA PM User Guide here.

C2000=For technical support on the C2000 please post your questions on The C2000 Forum. Please post only comments about the article PDK/PDK TDA PM User Guide here. DaVinci=For technical support on DaVincoplease post your questions on The DaVinci Forum. Please post only comments about the article PDK/PDK TDA PM User Guide here. MSP430=For technical support on MSP430 please post your questions on The MSP430 Forum. Please post only comments about the article PDK/PDK TDA PM User Guide here. OMAP35x=For technical support on OMAP please post your questions on The OMAP Forum. Please post only comments about the article PDK/PDK TDA PM User Guide here. OMAPL1=For technical support on OMAP please post your questions on The OMAP Forum. Please post only comments about the article PDK/PDK TDA PM User Guide here. MAVRK=For technical support on MAVRK please post your questions on The MAVRK Toolbox Forum. Please post only comments about the article PDK/PDK TDA PM User Guide here. For technical support please post your questions at http://e2e.ti.com. Please post only comments about the article PDK/PDK TDA PM User Guide here.

}}

Hyperlink blue.png Links

Amplifiers & Linear
Audio
Broadband RF/IF & Digital Radio
Clocks & Timers
Data Converters

DLP & MEMS
High-Reliability
Interface
Logic
Power Management

Processors

Switches & Multiplexers
Temperature Sensors & Control ICs
Wireless Connectivity

Retrieved from "https://processors.wiki.ti.com/index.php?title=PDK/PDK_TDA_PM_User_Guide&oldid=233538"