OMAPL1: Changing the Operating Point

Overview of operating point (OPP) support

Operating Point (OPP) is nothing but a recommended operating condition for the SoC defined by a voltage and frequency pair (V/F pair) for the core (CVDD).

On the OMAP-L1 (or DA8x, AM1x) SoCs, the following set of OPPs are supported by the ARM UBL:

1. 456MHz, 1.3V
2. 408MHz, 1.2V
3. 372MHz, 1.2V
4. 300MHz, 1.2V

The set of OPPs that are supported by the target SoC are documented in the SoC data sheet.

Configuring ARM UBL for a specific OPP

The ARM UBL can be configured to support one OPP at a time. The configuration is done at the time of building the ARM UBL.

The file include/device.h in ARM sources defines a set of macros - one for each OPP. These macros have been listed here for reference.

#define DEVICE_OPP_1P2V_300MHZ   0x00
#define DEVICE_OPP_1P2V_348MHZ   0x01 
#define DEVICE_OPP_1P2V_372MHZ   0x02
#define DEVICE_OPP_1P2V_408MHZ   0x03 
#define DEVICE_OPP_1P3V_408MHZ   0x04 
#define DEVICE_OPP_1P3V_456MHZ   0x05

To configure the UBL to a particular OPP one must set the define DEVICE_CONFIG_OPPOPP to one of the supported OPPs. For example, to configure UBL for (456MHz,1.3V) OPP:

#define DEVICE_CONFIG_OPP DEVICE_OPP_1P3V_456MHZ

CAUTION
Please refer to the data sheet for device you are using to make sure the OPP you are setting is actually supported by the device.

Changing OPP in Linux Kernel

On the DA850/OMAP-L138/AM1808 device, users can choose the maximum OPP to operate at from the Linux kernel. This is chosen during kernel configuration phase of kernel build process.

First enable CPU Frequency scaling (CPUFreq) feature of Linux kernel. The kernel uses this feature to change the OPP at runtime. Choose the performance governor if you just intend to operate at the highest OPP chosen.

CPU Power Management  --->
	[*] CPU Frequency scaling 
		<*>   'userspace' cpufreq policy governor
		Default CPUFreq governor (ondemand)  ---> 
			(X) performance 
Device Drivers  --->
	[*] Voltage and Current Regulator Support  --->    
		<*>   TI TPS6507X Power regulators

Now, select the maximum frequency the CPU should run at:

System Type  --->
	TI DaVinci Implementations  --->
		Select Maximum DA8xx/OMAP-L1/AM1xxx SoC speed (300 MHz)  --->
                          ( ) 300 MHz
                          ( ) 372 MHz
                          ( ) 408 MHz
                          (X) 456 MHz

Adding support for a new operating point (OPP)

In most use cases, the OPP pre-defined in PSP package should be sufficient. This section provides some general guidelines to help users add new OPP to the UBL code. These steps should be considered reference only. Depending on the OPP being added, the actual implementation may involve steps not documented here.

At a top level the following steps are required to add a new OPP:

1. Change the voltage supplied by the PMIC (Power Management IC) to the CPU (CVDD)
2. Change the the frequency generated by the CPU domain PLL (usually PLL0; please check with the device specific manual for the correct PLL number)
3. Configuration of EMIF interface timing parameters and frequency for the new OPP

   NOTE
   This step is required only of the changing the PLL configuration of CPU PLL also affects the EMIF interface.

Steps to add a new OPP to UBL:

1. Define a macro for the new OPP in include/device.h. Please refer to examples above
2. A new case should be added to the switch statement in LOCAL_getDeviceOPP() function in include/device.c, which returns the OPP configured based on the value of DEVICE_CONFIG_OPP
3. The src/device.c file contains functions for
   • PLL initialization
   • Memory Controller setup
   • Calls to PMIC setup function for setting a desired voltage.
   These functions are called from the DEVICE_init() function in src/device.c. The PLL initialization routines configure the required multiplier and divider ratios for various clock domains (like PLLDIVx for SYSCLKx, POSTDIV, PLL multiplier etc.).

For example, considering the case of adding (456MHz, 1.3v) OPP support newly:

1. Change the DEVICE_PLL0Init() in src/device.c as follows:
   • PLLM is configured to be 18 to generate 456MHz (24MHz * (18 + 1)) with a 24MHz OSCIN input.
   • POSTDIV is configured to 0 thus actual divsion is by one (0 + 1).
   • In case of DA830/OMAPL137/AM1707, the SDRAM controller (EMIFB) and the EMIFA controller are also running off PLL0. Thus changes to PLL0 also affect the the SDRAM controller and EMIFA controller settings. The input clock to the SDRAM controller and EMIFA controller should be appropriately set so as to not cross their max allowed limits (please refer to device specific data manual for this value). For example, for max EMIFA freq of 100MHz, the PLLDIV3 should be set to 4 so that SYSCLK3 is set to 456 / (4 + 1) = 91.2MHz. Also, the source for the EMIFA clock should be set to be from SYSCLK3 and not from DIV4P5.
2. Changes for the required voltage level:
   The required voltage level can be configured by calling the appropriate TPSxxx_set_DCDCy_voltage() function. Here, TPSxxx is the on board PMIC (example TPS65070) and DCDCy is the appropriate regulator that needs to be programmed (example DCDC3). Support for TPS65070 and TPS65023 is already provided. Please refer to the board schematics for the PMIC part number and the regulator (supplying the CVDD) that needs to be configured.
3. Changes for specific peripherals:
   Other change that is required is the SPI prescalar settings. Elements of board design, device and SPI slave capabilities put a cap at the maximum frequency at which the SPI bus can operate (say 30MHz). To ensure this, the SPI peripheral prescalar value must be adjusted. For example, at 456MHz CPU frequency, the SPI module frequency is 227MHz. Thus the prescalar should be set to 7 so that the SPI bus frequency does not cross 30MHz. Changes required for this are done in src/spi_mem.c