OMAP3 DSP MMU Configuration

What are TLBs?

The OMAP35xx MMU has Translation Lookaside Buffers (TLB). The TLB is a cache the allows the MMU to accelerate virtual to physical address translation by holding the most recent translations. For example if there is a TLB hit then the translation will be retrieved from the TLB cache. However, with a TLB miss the translation will have to be retrieved from the translation tables which would be a less optimal with regards to performance.

For detailed description of the MMU for OMAP35xx see the following manual.

• OMAP35x Memory Management Units Reference Guide

Who configures TLB entries?

The MMU TLB entries are configured by DSP/BIOS Link.

How are TLB entries configured?

DSP/BIOS Link adds TLB entries from the memory regions found in the memory tables of the LINKCFG_MemEntry array. When using Codec Engine, these DSP Link tables are automatically configured by Codec Engine.

See the DSP Link User's Guide found in the DSP LINK /dsplink/doc folder for more detailed information on LINKCFG_MemEntry.

See the PlatformGuide_OMAP3530.pdf found in the DSP LINK /dsplink/doc folder in 1.51 release for more information on the DSP MMU configuration and programming.

• https://www-a.ti.com/downloads/sds_support/TargetContent/link/index.html

What memory segments are mapped?

The memory segments added to DSP/BIOS Link LINKCFG_MemEntry array are mapped as TLB entries by DSP/BIOS Link. Codec Engine configures this array from the memory segments defined in the system memory map.

Referring to the example memory map below the following memory segments are mapped as TLB entries are:

• CMEM, DDRALGHEAP, DDR2, DSPLINK (MEM), DSPLINK (RESET), L4CORE, L4PER.

Address Range	Size	Description
0x80000000 - 0x84FFFFFF	80 MB	Linux
0x85000000 - 0x85FFFFFF	16 MB	CMEM
0x86000000 - 0x877FFFFF	24 MB	DDRALGHEAP
0x87800000 - 0x87DFFFFF	6 MB	DDR2 (BIOS, Codecs, Applications)
0x87E00000 - 0x87EFFFFF	1 MB	DSPLINK (MEM)
0x87F00000 - 0x87F00FFF	4 KB	DSPLINK (RESET)
0x87F01000 - 0x87FFFFFF	1020 KB	unused

Address Range	Size	Description
0x10F10000 - 0x10F17FFF	32 KB	CACHE_L1D
0x10E00000 - 0x10E07FFF	32 KB	CACHE_L1P
0x10800000 - 0x1080FFFF	64 KB	CACHE_L2
0x10F04000 - 0x10F0FFFF	48 KB	L1DSRAM
0x107F8000 - 0x107FFFFF	32 KB	IRAM - L2 RAM
0x48000000 - 0x48FFFFFF	16 MB	L4CORE: L4-Core Interconnect Address Space
0x49000000 - 0x490FFFFF	1 MB	L4PER: L4-Peripheral Interconnect Address Space

What are the rules for mapping memory segments?

• There are only 31 TLB entries locked for 4KB, 64KB, 1MB, and 16MB contiguous memory regions.

• Memory segments must be a multiple of 4KB.

• Adjacent memory must add up to a multiple of 4KB. Note smaller adjacent memory regions are grouped into a larger region which optimizes the number of TLB entries.

Example

Refering to the memory map above memory there will be 20 TLB entries:

• Number of entries of size 4KB: 1
• Number of entries of size 64KB: 0
• Number of entries of size 1MB: 16
• Number of entries of size 16MB: 3

Further Details

• L4CORE, L4PER

Memory regions are contiguous and a multiple of 4KB so they can be grouped together:

• addr: 48000000 - 0x490FFFFF
• size: 1100000 (17 MB)

The results are 2 TLB entries:

• Number of entries of size 1MB: 1
• Number of entries of size 16MB: 1

• CMEM, DDRALGHEAP, DDR2, DSPLINK (MEM), DSPLINK (RESET)

Memory regions are contiguous and a multiple of 4KB so they can be grouped together.

• addr: 85000000 - 0x87F00FFF
• size: 2f01000 (47MB + 4KB)

The results are 18 TLB entries:

• Number of entries of size 4KB: 1
• Number of entries of size 64KB: 0
• Number of entries of size 1MB: 15
• Number of entries of size 16MB: 2

Configuration errors

DSP link locks in 31 Translation look-aside Buffer (TLB) entries configured for 4KB, 64KB, 1MB, and 16MB contiguous memory regions. There is a potential to exhaust all to the 31 TLBs.

Example

• A region of size 0xFF000 (1MB - 4KB) results in 30 TLB entries of 15 x 64KB entries and 15 x 4KB entries. A 1MB region would result in one 1MB TLB entry. If more than 31 TLB entries are needed, a runtime configuration error is reported by DSP Link.

"Configuration error: Exceeded maximum number [31] of Translation Look- aside Buffers."

• Adjacent memory regions are not a multiple of 4KB

"Configuration error: Combined memory entries does not have a size that is a multiple of 4KB"

OMAP3 MMU FAQ's

How should I map memory in DSP address space?

To map some area into the DSP’s address space, user can call PROC_control API with respective commands from GPI side. Below shows a usage scenario of mapping an area into DSP’s address space.
Add the MMU entry:
<syntaxhighlight lang='c'> MemMapInfo mapInfo ; mapInfo.dspAddr = DSP_ADDR1 ; mapInfo.size = 0x80000  ;

status = PROC_control (ID_PROCESSOR,

                      PROC_CTRL_CMD_MMU_ADD_ENTRY,
                      &mapInfo);

</syntaxhighlight> Here PROC_CTRL_CMD_MMU_ADD_ENTRY is an enumerated type, directing GPP side logic to add user given entries to the DSP’s TLB. Now, User may want to write some information on the area, to be given to DSP. For this user has to map the area into GPP user/kernel address space. For this below example is useful:
<syntaxhighlight lang='c'> MemMapInfo mapInfo ; mapInfo.dspAddr = DSP_ADDR1 ; mapInfo.size = 0x80000  ;

status = PROC_control (ID_PROCESSOR,

                      PROC_CTRL_CMD_MAP_DSPMEM,
                      &mapInfo);

</syntaxhighlight> Once the user has done with his/her protocol, he/she may want to unmap the area from GPP and DSP address space as well. Below code how to achieve this: <syntaxhighlight lang='c'> Delete the MMU entry: MemUnmapInfo mapInfo ; mapInfo.dspAddr = DSP_ADDR1 ; mapInfo.size = 0x80000  ;

status = PROC_control (ID_PROCESSOR,

                      PROC_CTRL_CMD_UNMAP_DSPMEM,
                      &mapInfo);

status = PROC_control (ID_PROCESSOR,

                      PROC_CTRL_CMD_MMU_DEL_ENTRY,
                      &mapInfo);

</syntaxhighlight>

Please note that:

• Given size should be same at add and delete the dynamic entry.
• Can not remove a static entry dynamically.
• Given memory area to create a dynamic entry should be physically contiguous.
• These particular PROC_control() API calls should be performed after attaching to the DSP through PROC_attach(). When used in the Codec Engine environment, perform these calls after Engine_open() since Codec Engine performs PROC_attach() inside the Engine_open() API.