OMAP-L1x/C674x/AM1x SoC Architectural Overview

System Interconnect Overview

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The C674x DSP, ARM9 CPU Cores, System DMA, and device specific peripherals are interconnected within the OMAP-L1x devices by a low latency switch fabric. This switch fabric is described in detail in the subsequent articles.

The major components in the OMAP-L1x devices are:

• Masters (C674x DSP Megamodule, ARM9 CPU Core, EDMA3, select peripherals)
• Slaves (most peripherals, various memory controllers)
• Switched Central Resources (SCRs)
• Bridges and Buses

In each of the below diagrams the Masters (Transaction Initiators) are shown on the left hand side of the diagram, and the Slaves (Transaction Responders) are shown on the right hand side of the diagram. The switch fabric is shown in between the Masters and the Slaves as Switch Central Resources (SCRs) and Bridges (BRs).

The arrows indicate the master/slave relationship. Each arrow originates at a master and terminates at a slave (or group of slaves). The direction of the arrow does not indicate the direction of data flow. Data flow is typically bi-directional for each of the documented bus paths but there are minor exceptions. One example of an exception are the read/write ports of the EDMA3 Transfer Controller. The read port reads data from source memory/peripherals, and the write port writes data to destination memory/peripheral.

Some modules are shown on both sides of SCRs or have multiple instances in the block diagram. This is because select peripherals have both a Master DMA Port as well as one or more slave port(s). This dual port functtonality allows the peripheral to act as both a Master and and Slave. Examples include HPI, USB0, USB1, etc.

On chip/Off chip memory controllers are considered slave end points (targets) and are always shown on the right side of main SCRs. The memory controllers can be classified as one of the following

• stand alone memory controllers (such as Shared RAM or EMIF controllers)
• part of a module/peripheral (for example, system masters can access the C674x DSP Megamodule L1/L2 memory via the C784x DSP Megamodule Slave DMA Port (SDMA), and the EMAC CPPI RAM is accessible via the EMAC port shown on the right side of SCR1/SCR2.)
  

OMAP-L137 System Interconnect Diagram

OMAP-L138 System Interconnect Diagram

Master(s)

Masters (Transaction Initiators) in the OMAP-L1x device are IP modules which are capable of initiating their own read/write transfer requests. This includes both CPUs (ARM9 / C674x DSP Megamodule), System DMAs (EDMA3), and select peripherals that utilize their own Master DMA Ports to initiate their own read/write transfers.

The following Table lists the Masters for the respective OMAP-L1x devices

List of Masters on OMAPL1x/C674x/AM1x

Masters	Description	OMAP-L137	OMAP-L138	Default Master Priority*
ARM9-I	ARM9 Instruction:Instruction/Program accesses. I-Cache accesses	X	X	2
ARM9-D	ARM9 Data Port: Load/Store instructions, D-cache and peripheral register accessess	X	X	2
C674x DSP Megamodule Master DMA Port (MDMA)	C674x long distances memory access port (i.e. load/stores to external memory and shared RAM outside the DSP Mega Module Memory) and cache controller accesses to external memory and shared RAM. Note:MDMA is a "port" name, has no relation to EDMA3 or the DSP Megamodule IDMA.	X	X	2
C674x DSP Megamodule Configuration Port (CFG)	Provides access to the peripheral configuration bus. (i.e. accesses to McASP, PLLC, other Memory Mapped Peripherals)	X	X	2
Ethernet Media Access Controller (EMAC)	EMAC Master Port RX/TX DMA engine accesses to internal/external device memory	X	X	2
Universal Serial Bus Controller (USB2.0) (VBUS)	USB0 Queue Manager access to internal/external device memory	X	X	2
Universal Serial Bus Controller (USB2.0) (CDMA)	USB0 internal DMA Master Port: accesses to/from internal/external device memory	X	X	2
Universal Serial Bus Controller (USB1.0)	USB1 internal DMA Master Port: Accesses to/from internal/external device memory	X	X	2
Host Port Interface (HPI)	HPI Internal DMA Master Port: Accesses to/from device internal memory, external memory, and peripheral registers.	X	X	2
EDMA3_0_TC0 (RD)**	EDMA3_0 Transfer Controller 0 read accesses fromSRCperipheral/memory. EDMA3_0_CC0 Q0 submissions	X	X	0
EDMA3_0 Transfer Controller 0 (write)**	EDMA3_0 Transfer Controller 0 write accesses to DSP/peripheral/memory. EDMA3_0_CC0 Q1 submissions	X	X	0
EDMA3_0 Transfer Controller 1 (read)**	EDMA3_0 Transfer Controller 1 read accesses from SRC peripheral/memory. EDMA3_1_CC0 Q0 submissions	X	X	0
EDMA3_0 Transfer Controller 1(write)**	EDMA3_0 Transfer Controller 1 write accesses to DSP/peripheral/memory	X	X	0
EDMA3_0 Transfer Controller 0 (read)**	EDMA3_1 Tranfer Controller 0 read accesses from SRC peripheral/memory		X	0
EDMA3_1 Transfer Controller 1(write)**	EDMA3_1 Transfer Controller 0 write accesses to DST peripheral/memory		X	0
Liquid Crystal Display Controller (LCDC)	LCD DMA Port to read image data from external memory  OMAPL137/AM17xx/C6747: EMIFB SDRAM, OMAPL138/AM18xx/C6748: mDDR/DDR2	X	X	2
Programmable Realtime Unit 0 (PRU0)	PRU0 accesses to/from internal/external device memory and peripheral memory mapped registers (e.g McASP etc)		X	0
Programmable Realtime Unit 1 (PRU1)	PRU1 accesses to/from internal/external device memory and peripheral memory mapped registers (e.g McASP etc)		X	0
Seral ATA Controller (SATA)	SATA Tx/Rx FIFO Internal DMA port for accessing internal/external device memory		X	2
Video Port Interface (DMA 0)	VPIF01 Port to write to memory video data that is input from an external component		X	2
Video Port Interface (VPIF)(DMA 1))	VPIF02 Port to read from memory video data that will be output to an external component		X	2
Universal Parallel Port Controller (uPP)	uPP internal DMA Master Port: (DMA Channel I/Q)accesses to/from internal memory/external device memory to recieve/send data on uPPI/O bus		X	0

^**TCRD/WR priority cannot be programmed individually. Single priority value controls both TC rd/wr port priority.

Slaves

Slaves (Transaction Request Recipients) in the device are IP modules that accept / service the transfer requests from the masters. Modules that fall under this category are peripherals (such as SPI, McASP, McBSP, UART, I2C, etc) that rely on CPU or EDMA3 to initiate transactions on their behalf. On-chip memory (DSP L1/L2, ARM RAM, Shared RAM) and off-chip memory (SDRAM, DDR2/mDDR, NOR/NAND flash, etc) are also considered to be slave modules.

List of Slaves in OMAPL1x/C674x/AM1x Devices

Masters	Description	OMAP-L137	OMAP-L138
C674x DSP Megamodule Slave DMA Port (SDMA) <span style="color: rgb(0,0,255)" />	DSP SDMA port allows accessing only the DSP memories. DSPSS registers (e.g. program counter, IDMA, Cache controller, DSP Interrupt Controller, etc) are only accessible by DSP (other masters like ARM and HPI cannot access these registers)	X	X
ARM RAM	ARM RAM memory. On-chip/Internal memory	X	X
ARM ROM / ARM Interrupt Controller	ARM ROM and ARM interrupt controller (Only accessible by ARM)	X	X
Shared RAM	Accessible by ARM/DSP and all other masters (except LCDC)	X	X
EMIFA	SDRAM, NOR, NAND flash. Off-chip/External memory	X	X
EMIFB(SDRAM)	SDRAM. Off-chip/external memory	X	X
EMIFB(SDRAM)	SDRAM. Off-chip/external memory	X	X
mDDR/DDR2	mDDR/DDR2. Off-chip/external memory	X	X
Peripherals	Accesses to all peripheral memory mapped registers, including transmit/recieve registers for serial ports, DMA ports/FIFOs for peripherals like McASP/McBSP, PLL , PSC, master peripheral (EDMA, USB, SATA) configuration registers, etc.	X	X

NOTE: Not all masters can access all slaves. For additional details on restrictions, if any, on a particular master's accessibility to a given slave memory/peripheral on the device, please refer to the section on Master/Slave Connectivity.

Switched Central Resource (SCR)

Switch Central Resources provides low-latency interconnectivity between the masters and slaves. SCRs (also called Switch Fabric or crossbars) direct the access requests by providing address decoding, arbitration, and routing of the requests to the various slaves.

For uniquely exclusive master/slave pairs, concurrent transactions can be sent in parallel through and SCR. For example, if a request from the C674x Megamodule to configure the McASP and another request from the ARM to configure the UART arrive at a particular SCR concurrently, both of the requests will pass through the SCR at the same time.

The interconnect of a device typically consists of one or two main SCRs and a number of smaller, satellite SCRs. The main SCR's handle the majority of the traffic and are typically clocked at a higher frequency than the satellite SCRs.

The figure below illustrates one such data flow example, where the highlighted paths are completely independent of each other and will allow true concurrency and parallelism.

SCRconcurrent data movement 
 

Arbitration

Arbitration for the Switch Central Resources is a two layer arbitration scheme which occurs on the burst size boundary. Arbitration occurs when two competing resources attempt concurrent access to the same slave.

Layer 1: Master Priority Level Arbitration Each master in a device is assigned to a system priority level. Following a Power On Reset (POR), each masters priority level is reset to the its default as specified in the System Configuration (SYSCFG) Section of the device System Reference Guide.

All SCRs on the device perform arbitration based on the priority level of the master that sends the read/write access request. System programmers are expected to modify the default priority values in order to fine tune the system for their application requirements.

Level 0: Highest Priority Level
Level 1: 2nd Highest Priority Level
Level 2: 3rd Highest Priority Level
Level 3: 4th Highest Priority Level
Level 4: 5th Highest Priority Level
Level 5: 6th Highest Priority Level
Level 6: 7th Highest Priority Level
Level 7: Lowest Priority Level

If two concurrent requests to the same slave concurrently arrive from masters with different priority levels, the master with the highest priority level wins the arbitration.

Layer 2: Inter-Priority Level Aribitration

Inter-Priority Level Arbitration is implemented as round robin style arbitration. If two concurrent requests to the same slave arrive from masters with the same priority level, round robin arbitration decides which master is allowed to continue with the request, and which master must wait until the SCR is free before continuing with the request.

NOTE:Arbitration/Re-Arbitration occurs at burst size boundaries (or lower if a burst request is not used)

Default Burst Size

A transaction from a master is typically broken down into smaller bursts at the system interconnect level. This is done to increase the collective efficiency of transfers through the interconnect.

Since large burst sizes of higher priority threads will always win arbitration and subsequently block other low priority transactions until they are finished, It is assumed that the system programmer will fine tune the burst size of all the masters in the system. This allows the lower priority requests a chance to win arbitration between contiguous bursts of higher priority requests.

The default burst size for a master is shown in the table below.

Default Burst Size for Master Peripherals on OMAPL1x/c674x/AM1x

Master	Default Burst Size	Fixed/Configurable
DSP MDMA	Load/Store word/double word: 4 / 8 bytes Cache Victims (MDMA writes): 16 bytes Cache Misses (MDMA reads): 32 -128 bytes	Case Dependent
DSP CFG	Load/Store word/double word: 4/8 bytes	Case dependent
EDMA3_x_TCx	16/32/64 bytes	Configurable via CFGCHIPx register in the SYSCFG module
USB2.0	64 bytes	Fixed
HPI	4 words (16 bytes) for HPID accesses	Multiplexed mode w/ auto-increment reads/writes produce 4 word reads/writes. Multiplexed mode w/ non auto-increment reads/writes produce 1 word reads/writes.
EMAC	64 bytes	Fixed
VPIF	32/64/128/256 bytes	Configurable
SATA	32 bytes	Configurable (in words) 1/2/4/8 words

Bridges

Within the SoC/DSP, individual modules/peripherals/memories (or group of peripherals) may run at different clock rates and may have different bus width interfaces (typically 64 bit and 32 bit buses). Logic is needed to synchronize communication between two modules that operate at different clock rates and/or bus widths. Bridges provide the means of resolving these differences by performing bus-width conversion as well as bus operating clock frequency conversion.

Bridges are also responsible for buffering read and write commands and data. Buffering is implemented with First In First Out (FIFO) style buffering. One implication of this is that any high priority request that is passed into a bridge must wait until the bridge FIFO finishes its previous transactions before it is allowed to continue.

There are two types of Bridges:

• Synchronous Bridge: A bridge for which clock rates X and Y are either equal to, or are an integer multiple (i.e. "synchronous") of one another.
• Asynchronous Bridge: A bridge for which clock rates X and Y are asynchronous to each other. These bridges are typically used when a peripheral or group of peripherals have module clocks that are not an integer multiple of the primary (typically CPU) clocks (ex: 133MHz for EMIFA), or when modules are not constrained to a "fixed" ratio with respect to (w.r.t) the primary clocks (ex: The Async3 group of peripherals on OMAP-L138).

There are two main types of buses on the OMAP-L1x/c674x devices:

• A 64-bit bus with separate read and write interfaces, allowing multiple read and write transactions to occur simultaneously. This bus is best suited for high-speed/high-bandwidth exchanges, especially data transfers between on-chip and off-chip memories. On the OMAP-L1x/c674x family of devices, SCR1 interfaces with several modules using this 64-bit bus. Most of the high bandwidth master peripherals (ex: EDMA3 transfer controllers) and slave memories (ex: C64x+ system direct memory access (SDMA) port for L1/L2 memory access, mDDR/DDR2 controller, etc.) are directly connected to the main SCR through this 64-bit bus. Peripherals that do not support the 64-bit bus interface are connected to the main SCR via bridges (responsible for protocol conversion from a 64-bit to 32-bit bus interface).
  

NOTE: An exception to the above description of buses is the 32-bit bus connecting the EMIFB (SDRAM) controller to the main SCR on the OMAPL137/c6747 family of devices. Even though it is a 32-bit bus, it behaves like the 64-bit bus allowing multiple read and write transactions to occur simultaneously.

• A 32-bit bus with a single interface for both reads and writes. The read and write transactions are serviced strictly in order. This bus is best suited for communicating with the memory-mapped registers of all on-chip peripherals. On the OMAP-L1x/c674x family of devices, SCR2 interfaces with several modules using this 32-bit bus. Accesses to memory-mapped registers can be for configuration purposes (ex: accesses to configure a peripheral) or for data accesses (ex: read/writes from/to McASP receive/transmit buffer registers, and reads from the UART receiver buffer registers).

Master Slave Connectivity

Not all masters can access all slaves in the device. For a detailed description of which masters can access which slaves, refer to the System Interconnect chapter of the device specific System Reference Guide.