OMAP-L1x/C674x/AM1x LCD Controller (LCDC) Throughput and Optimization Techniques

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This article was created to present throughput measurements conducted on the LCD controller of OMAP-L1x/C674x/AM1xx devices. Different variables were explored to assess their impact on LCD controller performance. Finally, the maximum resolutions that can be achieved the LCD controller are also presented. 

The information in this article deals mainly with OMAP-L1x8/C674m/AM18xx devices (where m is an even number), however some data on OMAP-L1x7/C674n/AM17xx devices (where n is an odd number) is included in the presentations at the end of this article.

LCDC Overview

As its name implies, the LCD controller is used to interface OMAP-L1x8/C674m/AM18xx devices to LCD panels or similar devices. The LCD controller actually consists of two independent controllers: a raster controller and a LIDD controller. Only one controller can be active at a time.

• Raster Mode
  • RGB interface with clock and synchronization signals.
  • Typically used for graphics / color picture display.
  • Pixel size
    • 1/4/8 bits per color with palette
    • 12 or 16 (RGB565) bits per color without palette
  • Two sub-modes: active (TFT) and passive (STN).

• LIDD Mode
  • MPU interface (parallel or serial) to Motorola 6800/8080 family and Hitachi 44780 family.
  • Typically used for text display.
  • Asynchronous interface with programmable timings.
    

Note: Data in this wiki article deals only with Raster Mode.

More information on the LCD controller can be obtained from the TMS320C674x/OMAP-L1x Processor Liquid Crystal Display Controller (LCDC) User's Guide (SPRUFM0).

LCDC Clocking

The LCD controller internal logic is internally clocked from PLL0 SYSCLK2 which is always set to half the ARM or DSP frequency. In raster mode, the LCD controller derives an output clock, LCD PCLK, from SYSCLK2 using the formula PCLK = SYSCLK2/CLKDIV, where CLKDIV = 2 to 255. In LIDD mode, the LCD controller does not generate an output clock since this is an asynchronous interface. However, all LIDD mode timings are derived from an internal MCLK which is generated using the formula MCLK = SYSCLK2/CLKDIV, where CLKDIV = 2 to 255.

LCDC Data Movement

The LCD controller is a master peripheral. It has a dedicated DMA engine which reads data from external memory and writes it to the LCD controller data FIFO. The system DMA (EDMA) is not used by the LCD controller.

The LCD controller includes an internal data FIFO which is used in raster mode by the DMA to temporarily store data. The data FIFO has a programmable threshold (8 to 512 double words).

The LCD controller competes with other masters for access to external memory. The priority of the LCD controller and other master peripherals can be programmed through the master priority registers (MSTPRI0-3) in the System Configuration Module. Refer to the system reference guide for your device for more information on the master priority registers.

LCDC Throughput Characterization

A vast amount of throughput data was collected on the LCD controller. Several knobs (or variables) were turned to get a full understanding of the LCD controller throughput performance under different scnearios. The table below summarizes the variables that were explored.

One imporant variable that was considered during these throughput measurements was the impact of other master activity on the LCD controller throughput performance. To simulate activity generated by another master(s), a dummy EDMA continuous transfer was setup to compete for access to external memory. Several aspects of this backgound activity were also tweaked (see table below).

Throughput Data Test Variables

Test Variable	Options
DSP/ARM Frequency	300, 200, and 100 MHz
Pass/Fail Criteria	LCDC FIFO under runs and LCDC frame synchronization errors
LCDC Data Location	DDR2 (132 MHz)
Test Parameters	Raster Mode: active (TFT) and passive (STN) mode LCD pixel clock (PCLK) Bits Per Pixel: 16, 8 DMA FIFO threshold Background EDMA activity w/ different read rate levels & priority LCDC system priority DDR2 memory controller peripheral bus burst priority register (PBBPR) setting

Notes:

• The DMA FIFO threshold value shown in data below and in the slides is the minimum threshold value for which the test always passes for a given set of test parameters. A lower threshold value will cause the test to fail.
• No LIDD mode data was collected.
• All data collected using low-level software; BIOS and Linux were not used.
  

Test Environment

The following list describes the test environment under which the LCD controller throughput data was collected:

• All data was collected with the DSP & ARM running at three different frequencies: 300, 200, and 100MHz.
• The main type of memory used was DDR2, although some testing was done on mDDR.
  
• No drivers or high-level operating systems (BIOS, Linux, etc.) were used for this testing.  All data was collected using low-level software.
• Only Raster Mode was used, LIDD mode was not used.

Factors Affecting LCDC Throughput

As discussed above, the Raster controller has two modes: a passive mode and an active mode. Throughput data was collected for each mode under different conditions. The result of those measurements is included in the presentations below. In the OMAP-L1x8/C674m/AM18xx devices (where m is an even number), the only variable that makes an difference is the CPU frequency.  A decrease in CPU frequency leads to a decrease in the maximum PCLK frequency that can be achieved.  In the OMAP-L1x7/C674n/AM17xx devices (where n is an odd number), the limiting factor is DDR bandwidth.  As the PCLK frequency is increased, factors such as system priority and SDRAM memory controller bust priority start to become critical.

The table below summarizes the results of the passive mode data for OMAP-L1x8/C674m/AM18xx devices (where m is an even number).

Summary of Passive Mode Data

CPU/DDR Frequency (MHz)	Max PCLK Frequency (MHz)	Comments
300/132	37.5	LCDC throughput requirements are met under all conditions.
200/132	25	LCDC throughput requirements are met under all conditions.
100/132	12.5	LCDC throughput requirements are met under all conditions.

Notes:

• No difference observed in throughput with mDDR vs. DDR2.
• This number indicates the maximum PCLK observed during throughput measurement tests. It is possible that at a slightly higher PCLK frequency, the LCDC throughput requirements can still be met. However, due to test bench limitations, a sweep of different frequencies could not be performed.  Note: Observe all data sheet specifications regarding the maximum PCLK supported on your device.
  

The table below summarizes the results of the active mode data for OMAP-L1x8/C674m/AM18xx devices (where m is an even number).

Summary of Active Mode Data

CPU/DDR Frequency (MHz)	Max PCLK Frequency (MHz)	Comments
300/132	37.5	LCDC throughput requirements are met under all conditions.
200/132	50	LCDC throughput requirements are met under all conditions.
100/132	25	LCDC throughput requirements are met under all conditions.

Notes:

• No difference observed in throughput with mDDR vs. DDR2.
• This number indicates the maximum PCLK observed during throughput measurement tests. It is possible that at a slightly higher PCLK frequency, the LCDC throughput requirements can still be met. However, due to test bench limitations, a sweep of different frequencies could not be performed. Note: Observe all data sheet specifications regarding the maximum PCLK supported on your device.
  

Refer to the presentations below for results of the throughput measurements on OMAP-L1x7/C674n/AM17xx devices (where n is an odd number).

LCDC Maximum Resolution

LCD output can support a maximum display resolution up to 1024 x 1024 and a maximum supported pixel clock rate of 37.5 MHz.  The maximum frame rate that can be supported depends on the display resolution and pixel clock rate. Keep in mind that the display area must also account for blanking fields which are specified by the standard being used, i.e. VESA, CEA-861-D, etc.  An approximation for the maximum frame rate can be obtained by using the following formula:

max frame rate = PCLK / (X * Y * 1.3)

• PCLK is the pixel clock rate
• X is the resolution width
• Y is the resolution height
• 1.3 an approximation factor related to blanking times
  

The graphic shows the maximum frame rates that can be achieved when PCLK = 37.5MHz for several common display resolutions for OMAP-L1x8/C674m/AM18xx devices (where m is an even number).

LcdcResolutions37p5mhz.PNG

Notes:

• For approximation purposes only.
• Not all resolutions shown.
• Not indicative of BIOS and Linux LCD driver performance or supported features.
  
  

LCDC Throughput Presentation

The following presentation summarizes the results of all throughput measurements conducted on OMAP-L1x/C674x/AM1xx class of devices.

Omapl1x8_c674x_am18xx_lcdcThroughput.zip, where m is an even number.

Omapl1x7_c674n_am17xx_lcdcThroughput.zip, where n is an odd number.