How to use the AM335x IBIS Models

Introduction

The AM335x External Memory Interface is a very flexible interface which can be used with LPDDR, DDR2, DDR3, and DDR3L. There are many settings available to fine-tune the signal timing on this interface. These settings include ODT options, pullups, pulldowns, slew rate, etc. IBIS modeling can be used to fine tune the set of options for a given PCB. That said, understanding the mapping between the various IBIS models and the corresponding register configuration options is critical to doing this correctly. This article is intended to help bridge that gap so that AM335x users can properly model their memory interface and program the best options in the AM335x registers.

NOTE: TI does not support timing analysis with IBIS simulations. Rather, customers are encouraged to use the IBIS models for Signal Integrity (SI) analysis. As far as the timing goes, please follow the routing guidelines and length/skew matching requirements in the Data Manual.

IBIS Structure

Every pin on the device is listed with a corresponding "Selector". For example:

P1       DDR_DQS0                  Selector_1

If you then go and look at the definition of that Selector you will find all of the available models for that given I/O cell. For example:

[Model Selector] Selector_1
Model_1000 INPUT,1.5V,FULLTERM, 1.00*RExt,IND,5%,DIFF_VREF_FULLTERM_8MA_5PER_1P5
Model_1001 INPUT,1.5V,Half Thevenin, 1.60*RExt,IND,5%,DIFF_VREF_HALFTERM_5MA_5PER
Model_1002 INPUT,1.5V,FULLTERM, 0.88*RExt,IND,5%,DIFF_VREF_FULLTERM_9MA_5PER_1P5

Each of the models above corresponds to the I/O cell behavior given a specific set of configuration options.

Register Mapping

Parameters for a typical model

Each model has the following structure:

Reads

Model_xyz INPUT, <voltage>, <ODT>, <Impedance>, <Temperature>, <Voltage-tolerance>

Writes

Model_xyz 3-STATE, <voltage>, <ODT>, <slew>, <Impedance>, <Temperature>, <Voltage-tolerance>

Parameter	Options	Register Setting	TRM Reference
<voltage>	DDR3L (1.35V), DDR3 (1.5V), or DDR2/LPDDR (1.8V)
<ODT>	Reads:NOTERM_WEAK_PU_ON, NOTERM_WEAK_PD_ON, NOTERM_WEAK_PUPD_OFF, FULLTERM, Half Thevenin Writes: ODT Off	DDR_PHY_CTRL_1[reg_phy_rd_local_odt]	Table 7-254. DDR_PHY_CTRL_1 Register Field Descriptions
<slew>	fastest, fast, slow, slowest	ddr_cmd0_ioctrl, ddr_cmd1_ioctrl, ddr_cmd2_ioctrl, ddr_data0_ioctrl, ddr_data1_ioctrl ["sr" fields]	Table 9-7. DDR Slew Rate Control Settings
<Impedance>	0.67*RExt 0.73*RExt 0.8*RExt 0.88*RExt 1.00*RExt 1.14*RExt 1.33*RExt 1.6*RExt	ddr_cmd0_ioctrl, ddr_cmd1_ioctrl, ddr_cmd2_ioctrl, ddr_data0_ioctrl, ddr_data1_ioctrl ["I" fields]	Table 9-8. DDR Impedance Control Settings
<Temperature>	IND = -40 to 125C, 25C nominal		(In IBIS Comments)
<Voltage-tolerance>	(Power supply tolerance, not a register) 5% or 10%

Additional considerations for LPDDR vs DDR2

LPDDR and DDR2 are both 1.8V interfaces. However, they use different signaling technologies:

• LPDDR -> LVCMOS
• DDR2 -> SSTL

Let’s look at the pin DDR_D4 as an example…

N3       DDR_D4                    Selector_11

So here is the corresponding snippet from Selector_11:

|*****************************************************************************************
|     Usage I/O#1.35/1.5V/1.8V#X#X#BCSHTLTCSCDVPBFZ_SSDHV.PAD
|     Base model BCSHTLTCSCDVPBFZ_SSDHV
|*****************************************************************************************
[Model Selector] Selector_11

<snip>

Model_440 INPUT,1.8V,Pull-up/down off,IND,5%,VREF_NOTERM_PUPD_OFF_5PER_1P8

<snip>

Model_452 INPUT,1.8V,Pull-up/down off,IND,5%,LVCMOS_PUPD_OFF_5PER_1P8

Model_440 and Model_452 above are nearly identical, but that is because both LPDDR and DDR2 are 1.8V interfaces. The final field holds the difference between them. Model_440 is of type VREF_NOTERM which corresponds to DDR2 with no termination enabled (i.e. SSTL). Model_452 is of type LVCMOS, which is used for LPDDR.

The register mapping that corresponds to this selection in the actual hardware is ddr_io_ctrl[mddr_sel]:

• mddr_sel=0 -> DDR2/3 (SSTL)
• mddr_sel=1 -> LPDDR (LVCMOS)

Additional Notes on ioctrl Pin Mapping

The ioctrl registers map to the actual pins as follows:

Register[bits]	Signals
ddr_cmd0_ioctrl[9:5]	ddr_ck, ddr_ckn
ddr_cmd0_ioctrl[4:0]	ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]
ddr_cmd1_ioctrl[4:0]	ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn
ddr_cmd2_ioctrl[4:0]	ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1
ddr_data0_ioctrl[9:5]	ddr_dqs1, ddr_dqsn1
ddr_data0_ioctrl[4:0]	ddr_d[15:8], ddr_dqm1
ddr_data1_ioctrl[9:5]	ddr_dqs0, ddr_dqsn0
ddr_data1_ioctrl[4:0]	ddr_d[7:0], dqm0

Example

In AM335x EMIF Configuration tips the recommendation is to set all the IOCTRL registers to a value of 0x18B which breaks down as:

• SR[9:8] = 01 slow
• I[7:5] = 100 0.88*RExt
• SR[4:3] = 01 slow
• I[2:0] = 011 1.00*RExt

As an example, let's assume you would like to model this type of configuration for your own hardware. And let's assume for this example that you're using DDR3 (1.5V). Finally, we'll do this modeling using 5% power supply tolerance, though it could similarly be modeled using 10% tolerance (i.e. just choose the corresponding model).

The IOCTRL settings above correspond to the slew rate for ALL signals being set to "slow". The Impedance is being configured differently for some of the signals. The breakdown of signals controlled by these registers can be found in Table 9-9. DDR PHY to IO Pin Mapping. The register descriptions of the IOCTRL specifies which signals are affected by SR[9:8]/I[7:5]. So in particular, the following use 0.88*RExt:

• DQS
• DQSn
• CK
• CKn

Correspondingly the signals above should choose models with Impedance of 0.88*RExt. The others should use 1.00*RExt. So in this scenario we would use the following:

Signal	Model	Description
DQS	Model_655	3-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_PADP_5PER_1P5
DQS#	Model_847	3-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_PADN_5PER_1P5
CK	Model_343	3-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_5PER_1P5
CK#	Model_343	3-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_5PER_1P5
DQ	Model_352	3-STATE,1.5V,ODT off,slow, 1.00*RExt,IND,5%,SR01_8MA_5PER_1P5
DM	Model_352	3-STATE,1.5V,ODT off,slow, 1.00*RExt,IND,5%,SR01_8MA_5PER_1P5

Note that the write models always have ODT off since in that scenario ODT would be a function of the memory on the other side.  For reads, ODT would be the responsibility of AM335x and so that parameter is configurable for reads:

Signal	Model	Description
DQS	Model_1002	INPUT,1.5V,FULLTERM, 0.88*RExt,IND,5%,DIFF_VREF_FULLTERM_9MA_5PER_1P5
DQS#	Model_1002	INPUT,1.5V,FULLTERM, 0.88*RExt,IND,5%,DIFF_VREF_FULLTERM_9MA_5PER_1P5
CK	Model_343	3-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_5PER_1P5
CK#	Model_343	3-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_5PER_1P5
DQ	Model_496	INPUT,1.5V,FULLTERM, 1.00*RExt,IND,5%,VREF_FULLTERM_8MA_5PER_1P5
DM	Model_352	3-STATE,1.5V,ODT off,slow, 1.00*RExt,IND,5%,SR01_8MA_5PER_1P5

Note that the DDR_CK, DDR_CKN, and DDR_DQM pins are always driven by the AM335x (not the memory) which is why it is of type "3-STATE" (output) for both write and read operations above.

Verifying DDR Configuration

After investing the effort to determine the best models for your board, it will be up to the software team to actually make the necessary changes. This final and most critical step of the process is often done improperly! In order to simplify the process, a JTAG based script was created to read important registers on the device and parse the contents to show what's actually being used. Here's how to use download and use this script:

1. Download am335x-ddr-analysis.dss.
2. Launch CCS.
3. Create an appropriate target configuration file for connecting to your board.
   • File -> New -> Target Configuration File
   • Supply a name/location for the file.
   • View -> Target Configurations to see the available target configurations (yours should now be among them!).
   • Double-click your file in the Target Configurations panel to open it for editing.
   • Select your emulator and processor. Be sure to select a processor and not a board, as we don't want any gel files to be part of the configuration. Save.
4. Launch the debugger, but do not connect to any CPUs.
   • In the Target Configurations window, right-click on your ccxml file and select "Launch Selected Configuration"
5. Launch the scripting console by going to View -> Scripting Console.
6. Load am335x-ddr-analysis.dss in the scripting console by executing "loadJSFile <path-to-dss-file>/am335x-ddr-analysis.dss".
7. It will use the Debug Access Port (DAP) unobtrusively behind the scenes such that the Cortex A8 is never halted. It will generate a am335x-ddr-analysis_yyyy-mm-dd_hhmmss.txt file on your desktop.