FSYNC

Frame synchronization module (FSYNC)

Introduction

The Frame synchronization (FSYNC) module is used in the embedded processor TMS320C6474 to mark the boundaries of UMTS frames and system time in order to generate events synchronized with this time. The system’s clock control module sends synchronization and clock inputs to the FSYNC. Frame alignment is exported to external devices from the embedded processor via the SM_FRAME_CLK signal. The FSYNC module implements three sets of synchronization inputs:

1. FRAME_BURST and FSYNC_CLOCK pair for OBSAI RP1 compliant interface
2. UMTS_SYNC and UMTS_CLOCK pair, an alternative to the RP1 interface for synchronization to UMTS time. The antenna interface module uses this pair for CPRI synchronization mode. The beginning of a frame is set when a high true UMTS_SYNC pulse is captured on the rising edge of UMTS_CLK.
3. TRT and TRT_CLOCK pair, this pair is needed because the antenna interface driven by the RP3 timer runs at a derivative of a UMTS clock rate, hence UMTS_SYNC and UMTS_CLOCK. Since there may be non-UMTS standards that run at a different clock/sync rates, hence the introduction of TRT and TRT_CLOCK. Besides that, this pair is also used as an alternative to the RP1 interface for synchronization to system time. The system time boundary is marked during a high true TRT pulse captured on the rising edge of TRT_CLOCK.

In addition, FSYNC module also implements a watchdog timer, which is used to detect a failure of the RP1 interface to update synchronization within a programmable time. However, for the antenna interface in CPRI mode, the watchdog timer is not used. System and RP3 timers are separately maintained for system and frame alignment. Based on these timers, event generators are issued. Each event generator is software programmable and can be set either with system or with RP3 timer, from which the event generation is based. This program implements a range of event generators based on RP3 timer; hence only RP3 timer is used. These event generators are used primarily for system events generation and are usually programmed to give periodic strobes, which are positioned with a programmed delay. The resulting strobes are driven out on the system event lines.

Figure 10: Frame synchronization module block diagram

Non-RP1 Frame Synchronization

For interfaces other than OBSAI RP1, the C6474 must synchronize to the external UMTS frame or standard-specific alignment. The frame sync module input options are:

AIF Timer sync	AIF Timer clock	System Timer sync	System Timer clock	Intended use
frame_burst	fsync_clock	frame_burst	fsync_clock	RP1 or non-RP1 differential sync, differential clock
umts_sync	umts_clock	umts_sync	umts_clock	RP1 or non-RP1 single-ended sync, single-ended clock
umts_sync	fsync_clock	umts_sync	fsync_clock	RP1 or non-RP1 single-ended sync, differential clock
umts_sync	umts_clock	trt_sync	trt_clock	Non-RP1 or non-UMTS single-ended sync, single-ended clock

The antenna interface is configured with the third option; UMTS single-ended sync and Frame synchronization differential clock of 30.72 MHz. However, since only RP3 timer is used for the events generation, the system timer sync and clock are configured in functional test mode. For more information regarding the module input, refer to Frame Sync Configuration -> FSYNC configuration with non-RP1 interface.

Timer Configuration Concept

Figure 11: Timer configuration concept

The RP3 and system timers have four sections in timer configuration:

• Sub-chip (used to divide down the input reference clock)
• Chip count
• Slot count
• Frame count

Each section is controlled by terminal counts, where the C6474 writes by way of VBUS. The terminal count for the chip count section is unique in the way that it has a circular buffer of terminal counts. This circular buffer allows variable chip counts to accommodate variable slot sizes within a frame (in the case of the TD-SCDMA sub-frame). Counters will count up until they reach their respective terminal count values, and then wrap to zero. However, in the case of WCDMA, only one buffer terminal count is used, therefore the last buffer address would likely be programmed to zero.

Event generations

Events in the C6474 are generated owing to the thirty event generators. There are two mechanisms for triggering events: mask-based and counter based events.

Mask-based event generator

The mask-based events give the ability to generate UMTS trigger conditions of any 2n values of the sub-chip, chip, and chip terminal count address or frame by comparing the programmed trigger conditions to the RP3 UMTS timers. The trigger control consists of two registers: EGM_COMPARE, which is the trigger value register, and EGM_MASK, the trigger mask register, where the bits that should be compared are enabled. After the offset conditions have been met, a system event is generated when the bits in the EGM_COMPARE have the same value as the enabled bits. The resulting trigger is periodic. System events FSYNC_SYSEVNT0 – FSYNC_SYSEVNT9 and FSYNC_SYSEVNT18 – FSYNC_SYSEVNT29 are mask-based events. The minimum period of all events is 2 clocks, except the FSYNC_AIFRAMESYNC, SM_FRAME_CLK, FSYNC_SYSEVNT0 and FSYNC_SYSEVNT1, which have the minimum period of 8 clocks. These four events differ since there are special events:

• The FSYNC_AIFRAMESYNC event is generated directly from the antenna interface clock domain in order to avoid latency, and sent directly to the antenna interface. It has an associated VBUS synchronized event, FSYNC_SYSEVNT1 that may be used as a CPU event. An event is indicated when FSYNC_AIFRAMESYNC pulses high for a minimum of four clock cycles and is low for a minimum of four clock cycles.

• The SM_FRAME_CLK behaves the same manner as FRAME_AIFRAMESYNC, except that it is locally-clocked (with selected UMTS domain clock), associated to FSYNC_SYSEVNT0.

The mask-based events used in the TMS320C6474 are shown in the figures below:

Figure 12: Outbound data transfers from Tx processor to AIF outbound RAM

Figure 13: Inbound data transfer from AIF inbound RAM to Rx processor

Counter-based event generator

The counter-based event, as it is called, generates events using counters. The trigger value is programmed into the event generator\’s compare counter register, EGC_COUNTER. When a comparison is made for the sub-chip trigger value, the counter is incremented. This counter has a programmable count value of delay-1. When the counter reaches its full count (where it finishes to count until 0), an event is generated. System events FSYNC_SYSEVNT10-FSYNC_SYSEVNT17 are counter-based. In the program, the counter-based event is used for transferring control word from the Tx processor to AIF outbound RAM, FSYNC_SYSEVNT10 (as well as from the AIF inbound RAM to the Rx processor, FSYNC_SYSEVNT11) every 32 chips.

Frame synchronization module setup, fsync_setup.c

There are two functions in fsync_setup.c:

1. vConfigFsync() frame sync configuration
2. vCloseFsync() closing frame sync

Frame sync configuration, vConfigFsync()

<syntaxhighlight lang='c'>/************************************ Global variable definitions /</syntaxhighlight>
Global variable	Usage
CSL_FsyncHandle hFsync;	This is a pointer to the object CSL_FsyncObj, it is passed as the first parameter to all FSYNC CSL APIs.
CSL_FsyncObj myFsyncObj;	This object contains the reference to the instance of FYSNC. The pointer to this object is passed as FSYNC handles to all FSYNC CSL APIs.
CSL_FsyncMaskTriggerGenObj configMaskTrigger[FSYNC_NUM_ACTIVE_MASK_EVEN_GEN];	This object is used to specify a mask-based trigger event
CSL_FsyncCounterTriggerGenObj configCounterTrigger[FSYNC_NUM_ACTIVE_COUNTER_EVEN_GEN];	This object is used to specify a counter-based trigger event

<syntaxhighlight lang='c'>/************************************ Local variable definitions /</syntaxhighlight>
Local variable	Usage
CSL_FsyncSetup myFsyncCfg;	This is the setup structure to configure FSYNC using CSL_fsyncHwControl()
Uint16 terminalChipCount; CSL_FsyncTimerTermCountObj rp3TerminalCount, sysTerminalCount; CSL_FsyncTimerCountObj timerInit;	Terminal count setup: -CSL_FsyncTimerTermCountObj object is used to define RP3/System terminal counts in CSL_FsyncSetup -CSL_FsyncTimerCountObj object is used to query RP3/System/TRT timer count
CSL_Status status;	CSL status
CSL_BitMask16 ctrlArg;	Control argument for hardware command

<syntaxhighlight lang='c'>/************************************ RP3 Timer Configuration /</syntaxhighlight>
Variable	Usage
terminalChipCount = 2559;	Terminal chip count for RP3 terminal count configuration
rp3TerminalCount.lastSlotNum = 14;	Slot count = 15
rp3TerminalCount.lastSampleNum = 7;	Sub-chip number is 8 bits, chips are counted 1/8th chip increment
rp3TerminalCount.numChipTerminalCount = NUM_CHIP_COUNT_WRAP_WCDMA_FDD;	Number of chip terminal count in WCDMA is 1  NUM_CHIP_COUNT_WRAP_WCDMA_FDD = 1
rp3TerminalCount.pLastChipNum = &terminalChipCount;	Pointer to array containing terminal counts for chips = 2560

<syntaxhighlight lang='c'>/************************************ System Timer Configuration /</syntaxhighlight>
Variable	Usage
sysTerminalCount.lastSlotNum = 0;	System timer is not used for event generators, set slot count to 0
sysTerminalCount.lastSampleNum = 0;	System timer is not used for event generators, set sub-chip count to 0
sysTerminalCount.numChipTerminalCount = 0;	System timer is not used for event generators, set number of chip terminal count to 0
sysTerminalCount.pLastChipNum = NULL;	System timer is not used for event generators, set pointer to array containing terminal counts for chips to null

<syntaxhighlight lang='c'>/************************************ FSYNC Configuration with non-RP1 interface /</syntaxhighlight>
Variable	Usage
myFsyncCfg.syncRP3Timer = CSL_FSYNC_UMTS_SYNC;	RP3 timer sync source used is the UMTS (single-ended)
myFsyncCfg.syncSystemTimer = CSL_FSYNC_SYSTEM_TEST_SYNC;	System timer sync source used is the functional test mode since system timer will not be used for the event generators
myFsyncCfg.clkRP3Timer = CSL_FSYNC_FRAME_SYNC_CLK;	RP3 clock source for frame sync timers is defined as frame synchronization clock (differential clock)
myFsyncCfg.clkSystemTimer = CSL_FSYNC_VBUS_CLK_DIV_3;	System clock source for frame sync timers is defined as vbus_clock/3 for functional test mode
myFsyncCfg.pTerminalCountRP3Timer = &rp3TerminalCount;	Associate the RP3 terminal count timer with the pointer to RP3 timer configuration
myFsyncCfg.pTerminalCountSystemTimer = &sysTerminalCount;	Associate the System terminal count timer with the pointer to RP3 timer configuration
myFsyncCfg.systemTimerRp1Sync = CSL_FSYNC_RP1_TYPE_NOT_USED;	Since FSYNC is configuration with non-RP1 interface, RP1 sync system timer is not used
myFsyncCfg.rp3SyncDelay = 0;	Delay for RP3 sync in input clock cycles is defined as 0; this value can be up to 16 clock cycles
myFsyncCfg.systemSyncDelay = 0;	Delay for System sync in input clock cycles is defined as 0; this value can be up to 16 clock cycles
myFsyncCfg.todSyncDelay = 0;	Delay for Time of the Day in input clock cycles is defined as 0; this value can be up to 16 clock cycles
myFsyncCfg.rp3EqualsSysTimer = FALSE;	Boolean used to specify whether RP3 timer equals to System timer, in this case the RP3 and System timer are different
myFsyncCfg.syncMode = CSL_FSYNC_NON_RP1_SYNC_MODE;	Specify the sync mode; whether RP1(OBSAI) or non-RP1(CPRI)
myFsyncCfg.reSyncMode = CSL_FSYNC_NO_AUTO_RESYNC_MODE;	Specify whether auto resynchronization occurs whenever new sync is out of alignment
myFsyncCfg.crcUsage = CSL_FSYNC_USE_SYNC_BURST_ON_CRC_FAIL; myFsyncCfg.crcPosition = CSL_FSYNC_CRC_BIT_16_RCVD_FIRST;	CRC usage is only used in RP1 mode, thus these cases can be ignored in CPRI mode
myFsyncCfg.todLeapUsage = CSL_FSYNC_DONT_ADD_LEAPSECS;	Specify if time-of-day leap second is used. Since it is not present in CPRI mode, this case can be ignored.
yFsyncCfg.setupWatchDog.rp3FrameUpdateRate = 0; myFsyncCfg.setupWatchDog.wcdmaFrameUpdateRate = 0; myFsyncCfg.setupWatchDog.todFrameUpdateRate = 0;	The watchdog timer is only in used to detect a failure of the RP1 interface to update within a programmable time; these cases can be ignored in CPRI mode.
timerInit.frameNum = 0; timerInit.slotNum = 0; timerInit.chipNum = 0;	FSYNC time count initialization, used to query RP3/System/TRT timer count
myFsyncCfg.timerInit.pRp3TimerInit = &timerInit;	RP3 timer initialization
myFsyncCfg.timerInit.pSystemTimerInit = &timerInit;	System timer initialization

Mask-based events

1. AIF frame synchronization tick

AIF frame synchronization tick is a mask-based system event that occurs every 10 ms. The Tx MAC and Rx MAC modules use this tick in the AIF to synchronize with the inbound/outbound SERDES links.

<syntaxhighlight lang='c'>/************************************ Frame-sync tick / /* Mask-based trigger event to occur every frame (10msecs), for AIF frame sync. Used to synchronize the Rx/Tx SerDES links all mask bits are enabled to count until terminal count value /</syntaxhighlight> <syntaxhighlight lang='c'> configMaskTrigger[0].timerUsed = CSL_FSYNC_RP3_TIMER; configMaskTrigger[0].eventGenUsed = CSL_FSYNC_TRIGGER_GEN_1; configMaskTrigger[0].mask.frameMask = 0x0; configMaskTrigger[0].mask.slotMask = 0xFF; configMaskTrigger[0].mask.chipTerminalCountIndexMask = 0x0; configMaskTrigger[0].mask.chipMask = 0xFFFF; configMaskTrigger[0].mask.sampleMask = 0xFF; configMaskTrigger[0].offset.slotOffset = 0; configMaskTrigger[0].offset.chipTerminalCountIndex = 0x0; configMaskTrigger[0].offset.chipOffset = 0; configMaskTrigger[0].offset.sampleOffset = 0; configMaskTrigger[0].compareValue.slotValue = 0; configMaskTrigger[0].compareValue.chipTerminalCountIndexValue = 0x0; configMaskTrigger[0].compareValue.chipValue = 0; configMaskTrigger[0].compareValue.sampleValue = 0; </syntaxhighlight>

1. 8 chips tick for EDMA inbound data transfer

The DMA switch fabric is configured, to receive a tick every 8 chips, which allows PaRAM table configuration. This configuration is necessary for inbound data transfers from the AIF RAM to the external memory of the Rx processor (inbound data flow). This configuration allows an EDMA configuration to read 8 chips of data from all AxC when it receives a tick from the frame sync module.

<syntaxhighlight lang='c'>/************************************ 8 chips tick / /* Mask-based trigger event, inbound data transfer from AIF RAM -> Rx processor / configMaskTrigger[1].timerUsed = CSL_FSYNC_RP3_TIMER; configMaskTrigger[1].eventGenUsed = CSL_FSYNC_TRIGGER_GEN_4; configMaskTrigger[1].mask.frameMask = 0; configMaskTrigger[1].mask.slotMask = 0x0; configMaskTrigger[1].mask.chipTerminalCountIndexMask = 0; configMaskTrigger[1].mask.chipMask = 7; configMaskTrigger[1].mask.sampleMask = 0xFF; // lag of 8 chips between AIF write and EDMA read configMaskTrigger[1].offset.slotOffset =1; configMaskTrigger[1].offset.chipTerminalCountIndex = 0; configMaskTrigger[1].offset.chipOffset = 1; configMaskTrigger[1].offset.sampleOffset = 0; configMaskTrigger[1].compareValue.frameValue = 0x0; configMaskTrigger[1].compareValue.slotValue = 0x0; // don\’t care since there\’s only 1 terminal count in WCDMA configMaskTrigger[1].compareValue.chipTerminalCountIndexValue = 0; configMaskTrigger[1].compareValue.chipValue = 1; configMaskTrigger[1].compareValue.sampleValue = 0; </syntaxhighlight>

1. 4 chips tick for Protocol Encoder CPRI data construction

For each link, the frame sync module additional system events that strobe every four chips in time (CSL_FSYNC_TRIGGER_GEN_18-23). Each time the four chip of time has elapsed, the protocol encoder is enabled to process four chips of CPRI messages.

<syntaxhighlight lang='c'>/************************************ 4 chips tick / /* Mask-based trigger event, the PE is enabled every 4 chips to process CPRI messages. The PE ignores these signals until the frame synchronization strobes (CSL_FSYNC_TRIGGER_GEN_24-29) occurred for each link. CSL_FSYNC_TRIGGER_4_CHIPS: CSL_FSYNC_TRIGGER_GEN_18 for link 0 CSL_FSYNC_TRIGGER_GEN_19 for link 1 CSL_FSYNC_TRIGGER_GEN_20 for link 2 CSL_FSYNC_TRIGGER_GEN_21 for link 3 CSL_FSYNC_TRIGGER_GEN_22 for link 4 CSL_FSYNC_TRIGGER_GEN_23 for link 5 / configMaskTrigger[2].timerUsed = CSL_FSYNC_RP3_TIMER; configMaskTrigger[2].eventGenUsed = CSL_FSYNC_TRIGGER_4_CHIPS; configMaskTrigger[2].mask.frameMask = 0; configMaskTrigger[2].mask.slotMask = 0; configMaskTrigger[2].mask.chipTerminalCountIndexMask = 0x0; configMaskTrigger[2].mask.chipMask = 0x3; configMaskTrigger[2].mask.sampleMask = 0xFF; configMaskTrigger[2].offset.slotOffset = 0; configMaskTrigger[2].offset.chipTerminalCountIndex = 0; configMaskTrigger[2].offset.chipOffset = 0; configMaskTrigger[2].offset.sampleOffset = 0; configMaskTrigger[2].compareValue.frameValue = 0; configMaskTrigger[2].compareValue.slotValue = 0x0; // don\’t care since there\’s only 1 terminal count in WCDMA configMaskTrigger[2].compareValue.chipTerminalCountIndexValue = 0; configMaskTrigger[2].compareValue.chipValue = 1; configMaskTrigger[2].compareValue.sampleValue = 0; </syntaxhighlight>

1. 38400 chips strobe – Protocol Encoder frame synchronization strobe

The frame sync modules provides as well six frame synchronization strobes, one for each link (CSL_FSYNC_TRIGGER_GEN_24-29), intended to precede the Delta transmission timing of each link. The protocol encoder uses this 38400 chips strobe to mark the beginning of a frame. It only starts data construction when it receives these frame synchronization strobes. The four chips strobe time (CSL_FSYNC_TRIGGER_GEN_18-23) is ignored if it is not preceded by the frame synchronization strobe (CSL_FSYNC_TRIGGER_GEN_24-29).

<syntaxhighlight lang='c'>/************************************ 38400 chips strobe / /* Mask-based trigger event, frame synchronization strobe used by PE to mark the beginning of a frame. CSL_FSYNC_TRIGGER_38400_CHIPS: CSL_FSYNC_TRIGGER_GEN_24 for link 0 CSL_FSYNC_TRIGGER_GEN_25 for link 1 CSL_FSYNC_TRIGGER_GEN_26 for link 2 CSL_FSYNC_TRIGGER_GEN_27 for link 3 CSL_FSYNC_TRIGGER_GEN_28 for link 4 CSL_FSYNC_TRIGGER_GEN_29 for link 5 / configMaskTrigger[8].timerUsed = CSL_FSYNC_RP3_TIMER; configMaskTrigger[8].eventGenUsed = CSL_FSYNC_TRIGGER_38400_CHIPS; configMaskTrigger[8].mask.frameMask = 0; configMaskTrigger[8].mask.slotMask = 0xFF; configMaskTrigger[8].mask.chipTerminalCountIndexMask = 0; configMaskTrigger[8].mask.chipMask = 0xFFFF; configMaskTrigger[8].mask.sampleMask = 0xFF; configMaskTrigger[8].offset.slotOffset = 0; configMaskTrigger[8].offset.chipTerminalCountIndex = 0; configMaskTrigger[8].offset.chipOffset = 0; configMaskTrigger[8].offset.sampleOffset = 0; configMaskTrigger[8].compareValue.slotValue = 0; // don\’t care since there\’s only 1 terminal count in WCDMA configMaskTrigger[8].compareValue.chipTerminalCountIndexValue = 0; configMaskTrigger[8].compareValue.chipValue = 2; configMaskTrigger[8].compareValue.sampleValue = 0; </syntaxhighlight>

1. 4 chips tick for EDMA outbound data transfer

For outbound data transfer, the DMA switch fabric is configured, to receive a tick every 4 chips, which allows PaRAM table configuration. This configuration is used for outbound data transferring from the external memory of the Tx processor to the AIF RAM (outbound data flow). This configuration allows an EDMA configuration to read 4 chips of data for all AxC when it receives a tick from the frame sync module.

<syntaxhighlight lang='c'>/************************************ 4 chips tick / /* Mask-based trigger event for outbound data transfer from Tx processor -> AIF RAM / configMaskTrigger[14].timerUsed = CSL_FSYNC_RP3_TIMER; configMaskTrigger[14].eventGenUsed = CSL_FSYNC_TRIGGER_GEN_5; configMaskTrigger[14].mask.frameMask = 0; configMaskTrigger[14].mask.slotMask = 0; configMaskTrigger[14].mask.chipTerminalCountIndexMask = 0; configMaskTrigger[14].mask.chipMask = 0x3; configMaskTrigger[14].mask.sampleMask = 0xFF; // lag of 8 chips between AIF write and EDMA read configMaskTrigger[14].offset.slotOffset = 1; configMaskTrigger[14].offset.chipTerminalCountIndex = 0; configMaskTrigger[14].offset.chipOffset = 1; configMaskTrigger[14].offset.sampleOffset = 0; configMaskTrigger[14].compareValue.slotValue = 0; // don\’t care since there\’s only 1 terminal count in WCDMA configMaskTrigger[14].compareValue.chipTerminalCountIndexValue = 0; configMaskTrigger[14].compareValue.chipValue = 9; configMaskTrigger[14].compareValue.sampleValue = 0; </syntaxhighlight>

Counter-based events

1. 32 chips strobe for Control Word transfer (Tx processor -> AIF outbound RAM)

<syntaxhighlight lang='c'>/************************************ 32 chips strobe / /* Counter-based trigger event, the EDMA uses this event to transfer the control word every 32 chips from the Tx processor to AIF RAM / configCounterTrigger[0].timerUsed = CSL_FSYNC_RP3_TIMER; configCounterTrigger[0].eventGenUsed = CSL_FSYNC_TRIGGER_GEN_10; //event generator every 32 chips configCounterTrigger[0].eventCount = 4\*(SAMPLE_COUNT_WRAP_WCDMA_FDD+1)-1; configCounterTrigger[0].offset.slotOffset = 0; configCounterTrigger[0].offset.chipTerminalCountIndex = 0; configCounterTrigger[0].offset.chipOffset = 0; configCounterTrigger[0].offset.sampleOffset = 0; </syntaxhighlight>

1. 32 chips strobe for Control Word transfer (AIF inbound RAM -> Rx processor)

<syntaxhighlight lang='c'>/************************************ 32 chips strobe / /* Counter-based trigger event, the EDMA uses this event to transfer the control word every 32 chips from the AIF RAM to Rx processor / configCounterTrigger[1].timerUsed = CSL_FSYNC_RP3_TIMER; configCounterTrigger[1].eventGenUsed = CSL_FSYNC_TRIGGER_GEN_11; //event generator every 32 chips configCounterTrigger[1].eventCount = 4\*(SAMPLE_COUNT_WRAP_WCDMA_FDD+1)-1; configCounterTrigger[1].offset.slotOffset = 0; configCounterTrigger[1].offset.chipTerminalCountIndex = 0; configCounterTrigger[1].offset.chipOffset = 12; configCounterTrigger[1].offset.sampleOffset = 0; </syntaxhighlight>

The frame synchronization module configuration begins by initializing the CSL library, CSL_fsyncInit(NULL). This function initializes the CSL data structures and does not touch the hardware part of the module. Upon success, this function returns CSL_status CSL_SOK. The next step to accomplish is to open the instance of FSYNC requested, CSL_fsyncOpen(). The function call sets up the data structures for the particular instance of FSYCN device. The handle returned by this call is the input for the rest of the APIs used within the frame synchronization module. Once the FSYNC handle is returned successfully, setup operation is accomplished by calling the function CSL_fsyncHwSetup().

<syntaxhighlight lang='c'> /* Initialize CSL library, this step is required / CSL_fsyncInit(NULL); /* Open handle for link / hFsync = CSL_fsyncOpen(&myFsyncObj, CSL_FSYNC, NULL, &status); if ((hFsync == NULL) || (status != CSL_SOK)) { printf ("\nError opening CSL_FSYNC"); exit(1); } /* Do setup for Fsync / CSL_fsyncHwSetup(hFsync, &myFsyncCfg); </syntaxhighlight>

Upon setup completion, the event generators, as well as the timer are enabled:

Mask-based events enabled

<syntaxhighlight lang='c'> /* Mask-based trigger event generator 1 for frame sync tick every 10 ms / CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_CONFIG_MASK_BASED_TRIGGER_GEN, (void *)&configMaskTrigger[0]); CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_ENABLE_TRIGGER_GEN, (void *)&(configMaskTrigger[0].eventGenUsed)); </syntaxhighlight>

<syntaxhighlight lang='c'> /* Mask-based trigger event generator 4 (8 chip tick for inbound EDMA data transfer) / CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_CONFIG_MASK_BASED_TRIGGER_GEN, (void *)&configMaskTrigger[1]); CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_ENABLE_TRIGGER_GEN, (void *)&(configMaskTrigger[1].eventGenUsed)); </syntaxhighlight>

<syntaxhighlight lang='c'> /* Mask-based trigger event generator 5 (4 chip tick for outbound EDMA data transfer) / CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_CONFIG_MASK_BASED_TRIGGER_GEN, (void *)&configMaskTrigger[14]); CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_ENABLE_TRIGGER_GEN, (void *)&(configMaskTrigger[14].eventGenUsed)); </syntaxhighlight>

<syntaxhighlight lang='c'> /* Mask-based trigger event generator 18-23, the PE is enabled every 4 chips to process CPRI messages. / CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_CONFIG_MASK_BASED_TRIGGER_GEN, (void *)&configMaskTrigger[2]); CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_ENABLE_TRIGGER_GEN, (void *)&(configMaskTrigger[2].eventGenUsed)); </syntaxhighlight>

<syntaxhighlight lang='c'> /* Mask-based trigger event generator 24-29, frame synchronization strobe used by PE to mark the beginning of a frame. / CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_CONFIG_MASK_BASED_TRIGGER_GEN, (void *)&configMaskTrigger[8]); CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_ENABLE_TRIGGER_GEN, (void *)&(configMaskTrigger[8].eventGenUsed)); </syntaxhighlight>

Counter-based events enabled

<syntaxhighlight lang='c'> /* Counter-based trigger event generator 10, 32 chip strobe for control word transfer from Tx processor to AIF RAM / CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_CONFIG_COUNTER_BASED_TRIGGER_GEN, (void \*)&configCounterTrigger\[0\]); CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_ENABLE_TRIGGER_GEN, (void *)&(configCounterTrigger[0].eventGenUsed)); </syntaxhighlight>

<syntaxhighlight lang='c'> /* Counter-based trigger event generator 11, 32 chip strobe for control word transfer from AIF RAM to Rx processor / CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_CONFIG_COUNTER_BASED_TRIGGER_GEN, (void *)&configCounterTrigger[1]); CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_ENABLE_TRIGGER_GEN, (void *)&(configCounterTrigger[1].eventGenUsed)); </syntaxhighlight>

Timer enabled

<syntaxhighlight lang='c'> /* Enable timer / ctrlArg = 0; // this is a don\’t care value for timer enable CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_ENABLE_TIMER, &ctrlArg); </syntaxhighlight>

Closing frame synchronization module, vCloseFsync()

<syntaxhighlight lang='c'> /* Halt both RP3 and System timers by programming the FSYNC_CTL2_TIMER_HALT bit in the CTL2 register. / CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_HALT_TIMER, NULL); /* Disarm both Rp3 and System timers by clearing the FSYNC_CTL2_ARM_TIMER bit of the CTL2 register to stop generating events / CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_DISABLE_TIMER, NULL); hFsync->regs->CTL2 &= 0xFFFFFFFE; /* Disable all mask-based event generators / CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_DISABLE_TRIGGER_GEN, (void *)&(configMaskTrigger[0].eventGenUsed)); CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_DISABLE_TRIGGER_GEN, (void *)&(configMaskTrigger[1].eventGenUsed)); CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_DISABLE_TRIGGER_GEN, (void *)&(configMaskTrigger[2].eventGenUsed)); CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_DISABLE_TRIGGER_GEN, (void *)&(configMaskTrigger[8].eventGenUsed)); CSL_fsyncHwControl(hFsync, CSL_FSYNC_CMD_DISABLE_TRIGGER_GEN, (void *)&(configMaskTrigger[14].eventGenUsed)); /* Close the fsync handle / CSL_fsyncClose(hFsync); </syntaxhighlight>