EDMA FAQ for OMAPL13x C674x devices

EDMA FAQ for OMAPL13x/C674x devices

Overview

This wiki article is a collection of frequently asked questions (FAQ) on EDMA on OMAPL13x/C674x devices, along with some useful collateral and software reference links.

FAQ

Q. Could you please guide efficient EDMA setting to send 4Kbyte data from internal memory to DDR2 memory in OMAPL138?

Answer:

Usually, the read rate setting and default burst size (DBS) setting of the EDMA transfer controller can be varied to throttle the data rate of EDMA background transfers. The read rate setting can control the number of EDMA clock cycles between read command and the DBS setting specifies the maximum number of bytes per read command issued by the transfer controller. For more info. on the EDMA transfer configuration as well the data projected on % memory bandwidth utilization by EDMA activities with read rate variations for all DBS, please refer the below wiki:

http://processors.wiki.ti.com/index.php/EDMA_Background_Activity_for_OMAP-L1x/C674x/AM1x_Throughput_Measurements

In general, the max. EDMA throughput quoted is roughly 80-90% throughput possible from external memory (mDDR) or internal RAMs ... i.e. e.g. for DDR2 it would be 150 MHz x 2 (double data rate) x 2 (16 bits) = 600 Mbytes/sec but this throughput is for 4k buffer , A sync mode , Self chained & linking enabled EDMA configuration. Typically the best throughput you can get from EDMA would depend on the max throughput of the slower end point (source or dest) , so if you are doing L2 to EMIFA transfers, the best throughput possible will be max theoretical throughput achievable by EMIFA (and not L2) etc.

Q. Did the EDMA transfer controller would hang on read if BCNT=0? Is BCNT=0 valid?

Answer:

In general, BCNT should not be 0. For normal operation, valid values for BCNT are between 1 and 65 535 and a transfer with BCNT equal to 0 is considered either a null or dummy transfer.

For more info. on BCNT, please refer section 2.3.2.5 in the C645x EDMA3 user guide as below:

http://www.ti.com/lit/ug/spru966c/spru966c.pdf

For details on dummy/null completion conditions, please refer sections 2.3.5 & 2.5.3 from the above user guide.

Q. How to setup QDMA to request channel in C6748 and what is the mechanism to trigger QDMA event to initiate transfer?

Answer:

Unlike DMA, QDMA is not event /manual/chain triggered instead it is auto/link triggered. A QDMA transfer will be triggered when a CPU/EDMA3 writes to the trigger word of the QDMA channel parameter set (auto triggered) or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a specific QDMA channel (link triggered).

QDMA channels are typically for cases where a single event will accomplish a complete transfer since the CPU/EDMA3 would reprogram some portion of the QDMA PaRAM set in order to retrigger the channel. Usually QDMA transfer are programmed with CCNT = 1 for AB-synchronized transfers where CCNT number of TRs can be expected for ACNT × BCNT bytes each. For more details, please refer Table 16-4 & Section 16.2.4.3 in the C6748 TRM below.

Each DMA channel and QDMA channel can be independently programmed to map to a specific queue using the DMA queue number register n (DMAQNUMn) and the QDMA channel queue number register (QDMANUM) and the mapping of DMA/QDMA channels is critical in achieving the desired performance level for the EDMA. For more insight, please refer section 16.2.10 in C6748 TRM below:

http://www.ti.com/lit/ug/spruh79a/spruh79a.pdf

Q. Can we request "link" channel as similar to DMA/QDMA channels in C6748 to acquire live channel associated with unique PaRAM set to it?

Answer:

There is nothing like "link" channel to request and have only DMA/QDMA channels to request where as QDMA transfers requests can be link triggered to reload/update the non-null linked PaRAM sets for subsequent transfers. Actually, there is one to one mapping between DMA channel numbers and the PaRAM sets which are fixed and cannot be violated. Please refer Table 16-5 in TRM below but the mapping between the QDMA channels and the PaRAM sets can be programmed as per our choice in the QDMA channel n mapping register (QCHMAPn) in the EDMA3CC and the QDMA channels can be mapped to any of the PaRAM sets in the PaRAM memory map. But, by default, QDMA channels are mapped to PaRAM set 0. Please refer Figure 16-10 for QCHMAP & section 16.2.6.2 for more details.

http://www.ti.com/lit/ug/spruh79a/spruh79a.pdf

Q. If I am able to request a channel from EDMA handle instance 1 instead of handle instance 0, Can I still assign it to queue 0 or does handle instance 1 have a specific set of queues?

Answer:

By default, there is a one-to-one mapping between the queues and transfer controllers. So, the TRs associated with events in Q0 get submitted to TC0 and likewise, the TRs associated with events in Q1 will be submitted to TC1 respectively. An event that wins prioritization against other DMA/QDMA pending events would be placed at the end of the appropriate event queue. Always, a lower numbered queue has a higher dequeuing priority then a higher numbered queue. Please refer section 16.2.10 Event queue in TRM. So, each edma handle instance would be mapped to specific event queue based on event prioritized requests from different peripherals/external hardware which will not allow handle instance 1 to assign it to event queue 0.

Q. If I want to do 2 bytes at a time until the buffer size is reached and then interrupt me when I have a complete buffer. How does one accomplish this in OMAPL138?

Answer:

Yes, it is possible through ping pong buffer mechanism which would transfer 2 bytes one at a time until it reaches the full buffer capacity and then it interrupts once when it completes the buffer. This is the approach used in EDMA LLD and you have the test code for DMA ping pong buffer approach. May be, you could download MCSDK which supports ping pong buffer approach of EDMA transfer.

MCSDK would support both SYS/BIOS and Linux OS for OMAP-L138 LCDK platform and to install the latest MCSDK product release, please refer the below link:

http://www.ti.com/tool/bioslinuxmcsdk

To get started with MCSDK, please refer the below MCSDK user guide:

http://processors.wiki.ti.com/index.php/MCSDK_User_Guide_for_OMAPL138

Q. I am having a hard time finding a clear explanation about what FIFO mode is and when to use it?

Answer:

The destination (Dst) FIFO register set stores the context for the DMA transfer requests currently in progress or pending in the write controller and the data FIFO holds temporary in-flight data. The source peripheral's read data is stored in the data FIFO and subsequently written to the destination peripheral/end point by the write controller. For more details on FIFO mode usage in EDMA3, please refer section 16.2.1.2 in TRM below:

http://www.ti.com/lit/ug/spruh79a/spruh79a.pdf

Q. What is the significance of BCNTRLD value in EDMA PaRAM Set and what this value is used for ?

Answer:

BCNT reload (BCNTRLD) is the count value used to reload BCNT when BCNT decrements to 0 which is only applicable for A-synchronized transfers. For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the EDMA3TC decrements BCNT appropriately and BCNTRLD is not used. For details, please refer Section 16.2.3.2.7 & see Table 16-3 for parameter updates in EDMA3CC in TRM below for a non null PaRAM set.

http://www.ti.com/lit/ug/spruh79a/spruh79a.pdf

Q. Do we have any tutorial for EDMA3 LLD API to program for various types of transfers?

Answer:

The objective of the below tutorial to analyze LLD examples for basic transfers, interrupt generation, linking, channel sorting, chaining, etc.

Online Training: EDMA training

Please refer to the following link.

http://processors.wiki.ti.com/images/5/5e/EDMA3_LLD.pdf

http://processors.wiki.ti.com/index.php/Programming_the_EDMA3_using_the_Low-Level_Driver_%28LLD%29

Q. How can I troubleshoot to find out whether the PaRAM Sets are correctly linking even after interrupt is fired correctly?

Answer:

In general, DMA PaRAM set would be updated after each Tx/Rx DMA transfer for the next buffer to receive or send, updates the current PaRAM set and update the next buffer to send/receive.

We could type the address of variable as "&paramSet" in the memory browser window of CCS debugger and we could be able to watch the values of all structure members of the paramSet pointing to structure "EDMA3CCPaRAMEntry" in the consecutive memory locations corresponding to declared data type size configuration. By this way, we could also ensure the memory dump of paramSet object pointing to structure members through which, we could validate the member "linkAddr" of linking second PaRAM set in a case even after interrupt is fired correctly. This would probably identifies whether we have linking issue happens with second PaRAM set after first Tx./Rx. DMA transfer appropriately.

Q. Are there any method to speedup the access of the EDMA register?

Answer:

Usually, the read rate setting and default burst size (DBS) setting of the EDMA transfer controller can be varied to throttle the data rate of EDMA background transfers. The read rate setting can control the number of EDMA clock cycles between read command and the DBS setting specifies the maximum number of bytes per read command issued by the transfer controller. For more info. on the EDMA transfer configuration as well the data projected on % memory bandwidth utilization by EDMA activities with read rate variations for all DBS, please refer the below wiki:

http://processors.wiki.ti.com/index.php/EDMA_Background_Activity_for_OMAP-L1x/C674x/AM1x_Throughput_Measurements

In general, the max. EDMA throughput quoted is roughly 80-90% throughput possible from external memory (mDDR) or internal RAMs ... i.e. e.g. for DDR2 it would be 150 MHz x 2 (double data rate) x 2 (16 bits) = 600 Mbytes/sec but this throughput is for 4k buffer , A sync mode , Self chained & linking enabled EDMA configuration. Typically the best throughput we can get from EDMA would depend on the max. throughput of the slower end point (source or destination), so if we are doing L2 to EMIFA transfers, the best throughput possible will be max theoretical throughput achievable by EMIFA (and not L2) etc.

Q. Is it possible to implement receive timeout in DMA FIFO mode using UART?

Answer:

We could use LSR in which if the DR bit is set and the corresponding interrupt enable bit is set (ERBI = 1 in IER), an interrupt request would be generated which indicates the data ready for the receiver. Refer Table 30-17 from the TRM below:

We do think, there is a ERBI field in IER which can be enabled so that it gives the provision to enable receiver data available interrupt and character timeout indication interrupt. Kindly refer Table 30-9 from the TRM below:

http://www.ti.com/lit/ug/spruh79a/spruh79a.pdf

As well, in the non-FIFO mode, when a character is placed in RBR and if the receiver data-ready interrupt is enabled in IER, an interrupt would be generated. This interrupt would be cleared when the character is read from RBR.

In the FIFO mode, the same interrupt would be generated when the FIFO is filled to the trigger level selected in the FIFO control register, and it would be cleared when the FIFO contents drops below the trigger level. For more information, kindly refer section 30.3.1 from the above doc.