EDMA FAQ for KeystoneI/II devices

EDMA FAQ for KeystoneI/II devices

Overview

This wiki article is a collection of frequently asked questions (FAQ) on EDMA on KeystoneI/II devices, along with some useful collateral and software reference links.

FAQ

Q. Where are software and hardware documentation resources located?

Answer

TI provides key software components (Processor SDK, MCSDK) for both Linux and TI-RTOS platforms and documentation from the tools & software page:

http://www.ti.com/lsds/ti/processors/dsp/c6000_dsp-arm/66ak2x/tools_software.page

You can also download the development tools, technical documents, training & videos for 66AK2x platforms.

For the complete list of software, refer the software section for the platforms as shown:

66AK2Ex: http://www.ti.com/product/66AK2E05/toolssoftware#softTools

66AK2Hx: http://www.ti.com/product/66AK2H12/toolssoftware#softTools

66AK2Lx: http://www.ti.com/product/66AK2L06/toolssoftware#softTools

Keystone II platform hardware schematic/block diagram, BOM, reference guide, Gerber files, etc. are available here:

66AK2E: http://www.ti.com/product/66AK2E05/toolssoftware#TIDesigns

66AK2G: http://www.ti.com/product/66AK2G02/toolssoftware#TIDesigns

66AK2L: http://www.ti.com/product/66AK2L06/toolssoftware#TIDesigns

The key software components (Processor SDK for TI-RTOS platform, MCSDK for both Linux and TI-RTOS platforms) are available for C667x & C665x Keystone I platforms. To get tools and software for C66x Multi-Core DSPs, refer the pages below:

C66x: http://www.ti.com/lsds/ti/processors/dsp/c6000_dsp/c66x/tools_software.page

Keystone I platform hardware schematic/block diagram, BOM, reference guide, Gerber files, etc. are available here:

C6678: http://www.ti.com/product/TMS320C6678/toolssoftware#TIDesigns

C6657: http://www.ti.com/product/TMS320C6657/toolssoftware#TIDesigns

For the complete list of software, refer the software section for the platforms as shown:

C6678: http://www.ti.com/product/TMS320C6678/toolssoftware#softTools

C6657: http://www.ti.com/product/TMS320C6657/toolssoftware#softTools

Q. What is the functional description of the EDMA hardware blocks?

Answer

The primary purpose of the Enhanced Direct Memory Access (EDMA3) Controller is to service data transfers between two memory-mapped endpoints on a device. EDMA3 Module consists of EDMA3 Channel Controllers (EDMA3CC) and EDMA3 Transfer Controllers (EDMA3TC).

The EDMA3 Channel Controller serves as the user interface for the EDMA3 Controller. The EDMA3CC includes set of Parameter RAM (PaRAM), channel control registers, and interrupt control registers. The EDMA3CC prioritizes incoming software requests or events from peripherals and submits Transfer Requests (TR) to the EDMA3 Transfer Controller.

The EDMA3 transfer controllers are responsible for data movement. A Transfer Request Packet (TRP) submitted by the EDMA3CC contains the transfer context. Based on the TRP, the transfer controller issues a read or write command that includes source and destination addresses and other transfer parameters.

For more details of the main blocks of EDMA3CC and EDMA3TC, including functional block diagrams, refer to sections 2.1.1, 2.1.2, 2.1.3 of KeyStone Architecture Enhanced Direct Memory Access (EDMA3) Controller User's Guide.

Q. What are EDMA3 channel types and how does the EDMA3 transfer happen?

Answer

The EDMA3CC includes two channel types:

• DMA channels
  

• QDMA channels
  

Each channel is associated with a given event queue/transfer controller and with a given Parameter Ram (PaRAM).

A trigger event is necessary to initiate a transfer. For DMA channels, a trigger event may be an external event, manual write to the event set register, or chained event. QDMA channels are auto-triggered when a write is performed to the user-programmed trigger word in the PaRam.

Once a trigger event is recognized, the channel that is associated with the event is queued in the appropriate EDMA3CC event queue.

Each event in the event queue is processed in a FIFO order. On reaching the head of the queue, the PaRAM associated with that channel is read to determine the transfer details. The Transfer Controller (TC) submission logic evaluates the validity of the Transfer Request (TR) and is responsible for submitting a valid TR to the appropriate EDMA3TC.

The EDMA3TC receives the request and is responsible for data movement as specified in the Transfer Request Packet (TRP). Other necessary tasks, like buffering and ensuring transfers, are carried out optimally wherever applicable.

The EDMA3TC can be configured to generate an event either when the transfer is complete or when the CC starts the transfer. The event that is generated can be used to generate interrupt to a CPU or for chaining (see below). Additionally, the EDMA3CC has an error detection logic that causes an error interrupt generation on various error conditions (For example, missed events, exceeding event queue thresholds, etc.)

Q. What is a Parameter Ram (PaRam) and how is the PaRam set organized?

Answer

The set of PaRams gives the user the ability to pre-configure multiple transfer parameters during initialization to minimize application execution time. Each PaRam is an 8-byte structure that contains transfer context (source/destination addresses, count, indexes, etc.). To facilitate transfer, each PaRam is associated with a DMA or QDMA channel. Before channel transfer starts, the PaRam that is associated with the channel is loaded into the TC.

Details on EDMA3 channel parameter description are provided in Figure 2-7 and Table 2-2 of KeyStone Architecture Enhanced Direct Memory Access (EDMA3) Controller User's Guide.

Q. What are EDMA3 channel controller regions and how are shadow region registers interpreted with each EDMA3 shadow region associated with its memory map?

Answer

The EDMA3 channel controller (EDMA3CC) divides its address space into multiple regions. Individual channel resources are assigned to a specific region, where each region is used by a different part of the execution. So it is easy to control the distribution of EDMA resources.

The EDMA3CC memory-mapped registers are divided in three main categories:

1. Global registers

2. Global region channel registers

3. Shadow region channel registers

The global registers are located at a single/fixed location in the EDMA3CC memory map. These registers control EDMA3 resource mapping and provide debug visibility and error tracking information.

The channel registers (including DMA, QDMA, and interrupt registers) are accessible via the global channel region address range, or in the shadow n channel region address ranges. Refer to Table 2-7 & Figure 2-12 of KeyStone Architecture Enhanced Direct Memory Access (EDMA3) Controller User's Guide for shadow region registers. Figure 2-12 provides the offset of the shadow registers in the EDMA3 controller block. The global addresses of each EDMA controller can be found in the memory map section of the appropriate device User's Guide.

Q. What are the software building blocks: EDMA LLD, EDMA CSL, and StarterWare?

Answer:

TI provides multiple levels of APIs (Application Programming Interface) to drive the EDMA:

• StarterWare is a basic library to manipulate EDMA that does not require any operating system.
  

• CSL is part of the TI-RTOS operating system and provide low-level EDMA drivers.
  

• EDMA LLD is a set of APIs that abstract details of the implementation and make it easy for the user to use EDMA.
  

In addition devices that run LINUX on ARM have a set of LINUX drivers that control the EDMA.

EDMA3LLD:

The EDMA3 Low-Level Driver (LLD) is a set of APIs that supports programming the EDMA3 peripheral. EDMA3 LLD is a component of the Processor SDK RTOS. EDMA3 LLD has two modules:

• The driver module (drv) contains APIs for configuration and run-time operation of the EDMA3.
  

• The resource manager (rm) module contains APIs to manage the usage of various EDMA3 resources across multi-processor devices.

The EDMA3 User's Guide and API description is part of the doc directory (\edma3_lld_2_12_01_24\packages\ti\sdo\edma3\drv\docs for the drv and \edma3_lld_2_12_01_24\packages\ti\sdo\edma3\rm\docs for the rm). Example projects that demonstrate how to use the EDMA3 LLD are part of the examples directory (\edma3_lld_2_12_01_24\examples)

CSL:

Chip Support Library (CSL) is part of Programmer Development Kit (PDK). CSL contains sets of low-level drivers to manipulate hardware component of the device, including EDMA3. The file csl_edma3Aux.h in directory \pdk_c667x_2_0_2\packages\ti\csl (release version may vary) contains the APIs that can be used by an application as well as other include files edma3.h and edma.h. The source code for the csl EDMA3 is in directory \pdk_c667x_2_0_2\packages\ti\csl\src\ip\edma\V0 (see V1 as well, release version varies). Some of the CSL EDMA3 APIs are inline functions as part of the csl_edma3Aux.h.

StarterWare:

StarterWare is a free software development package that provides no-OS platform support for ARM and DSP TI processors. StarterWare includes Device Abstraction Layer (DAL) libraries, peripheral programming, and board level example applications that demonstrate the capabilities of the peripherals on the TI processors. StarterWare can be used stand-alone or with an RTOS.

Note: There is no StarterWare support available for Keystone I/II devices. The StarterWare support is only available for single-core DSP devices and is intended to support multiple processors of the TI SoC family, such as AM1808, OMAPL138, C6748, and AM335x.

Q. Where is EDMA3 software (LLD, CSL, and StarterWare) located in the releases?

Answer:

EDMA3LLD:

EDMA3 LLD is part of Processor SDK RTOS perspective. Processor SDK can be downloaded from the appropriate device location:

*     Processor SDK for AM335x
*     Processor SDK for AM437x
*     Processor SDK for AM57xx
*     Processor SDK RTOS for C665x
*     Processor SDK RTOS for C667x
*     Processor SDK RTOS for K2E
*     Processor SDK RTOS for K2G
*     Processor SDK RTOS for K2H/K2K
*     Processor SDK RTOS for K2L

The standalone EDMA3 LLD can be downloaded from the EDMA3 Low-level Driver Product Download Pages.

EDMA3 CSL:

CSL is part of the PDK package that is included in the Processor SDK RTOS release. The include files are in the $(TI_PDK_INSTALL_DIR)\packages\ti\csl directory, where $(TI_PDK_INSTALL_DIR) is the PDK directory of the Processor SDK RTOS. Source files are in $(TI_PDK_INSTALL_DIR)\packages\ti\csl\src\ip\edma\V0. EDMA examples are found here: $(TI_PDK_INSTALL_DIR)\packages\ti\csl\example

StarterWare:

StarterWare releases for the devices that are supported can be downloaded from the StarterWare Wiki.

Q. Where are EDMA3 ARM Linux drivers for KeyStone devices located?

Answer

Linux EDMA3 drivers are part of TI Linux release and Real-Time (RT) Linux release for KeyStone family devices and some of the Sitara family devices. The latest version of Linux release can be found here.

The EDMA3 drivers are part of the Linux Kernel. The EDMA3 drivers APIs are defined in the dma.h include file. This include file and other dma include files are located in /processorSDKLINUX_XX_XX_XX_XX/board-support/linux-4.4.12+gitAUTOINC+3639bea54a-g3639bea54a/arch/arm/include/asm, where processorSDKLINUX_XX_XX_XX_XX is the directory where the LINUX release was installed.

Note that the translation between logical and physical addresses for devices with EDMA3 controllers that do not have unified MMU (Memory Management Unit) is done using MPAX (Memory Protection and Extension) registers and not MMU.

Q. What is a 1D, 2D, 3D EDMA3 transfer and how are the transfers configured?

Answer:

EDMA3 can move 1D, 2D or 3D arrays:

• 1D transfer moves 1D vector. That is, the transfer moves ACNT (A Count) bytes from source address to destination address.
  

• 2D transfer is used to move matrices. That is, the channel moves ACNT bytes to the destination, then it skips DSTBIDX (Destination B Index) bytes and SRCBIDX (Source B Index) in the destination, and again moves ACNT bytes. The process is repeated BCNT (B Count) times. The 2D configuration can be on the source address or destination address or both.
  

• 3D transfer moves multiple matrices. That is, it moves a matrix with the parameters from above (2D transfer), then it skips DSTCINX (Destination C Index) or SRCDINX (Source C Index) or both and moves the next matrix. The process repeats itself CCNT (C Count) times.
  

A collection of EDMA3 transfer example configurations are included in the Processor SDK release and can be found in \edma3_lld_2_12_01_24\examples (version number may vary).

Q. What is the difference between DMA and QDMA channels?

Answer:

QDMA channels and DMA channels transfers are configured by the PaRams. The difference between DMA and QDMA channels is the event/channel synchronization:

• QDMA events are either auto-triggered or link triggered. Auto-triggering allows QDMA channels to be triggered by a CPU with a single write to the PaRAM. Link triggering allows a linked list of transfers to be executed using a single QDMA PaRAM set and multiple link PaRAM sets.
  

• DMA channels are triggered by an event. Events can be generated by an internal component like a CPU, an EDMA channel linking another component, or by an external device using an interface such as SRIO (Serial Rapid IO) or PCIe (Peripheral Component Interconnect Express).

Q. What APIs can be used in EDMA3 LLD, EDMA3 CSL, and StarterWare?

Answer:

EDMA3LLD:

The EDMA3 Resource Manager User Guide is in the directory dma3_lld_X_XX_XX_XX\packages\ti\sdo\edma3\rm\docs where dma3_lld_X_XX_XX_XX is the directory where EDMA3 was installed. The same directory has a chm system of description of all APIs.

The EDMA3 Driver APIs User Guide is in directory dma3_lld_X_XX_XX_XX\packages\ti\sdo\edma3drv\docs where dma3_lld_X_XX_XX_XX is the directory where EDMA3 was installed. The same directory has a chm system of description of all APIs.

EDMA3 CSL:

A complete list of CSL EDMA3 API functions can be found pdk_YYY_X_X_X\packages\ti\csl\docs\doxygen\html/group___c_s_l___e_d_m_a3___f_u_n_c_t_i_o_n.html where pdk_YYY_X_X_X is the directory where PDK was installed.

StarterWare:

StarterWare documents including a chm system of description of all StarterWare APIs can be found in directory \pdk_YY_X_X_X\packages\ti\starterware\docs where pdk_YY_X_X_X is the directory where PDK was installed. Note that StarterWare is available only for subset of Sitara devices.

The EDMA StarterWare include file edma.h is in directory \pdk_YY_X_X_X\packages\ti\starterware\include and the source code file edma.c is in the directory \pdk_YY_X_X_X\packages\ti\starterware\dal

Q. How do you configure EDMA from Linux using Linux drivers API?

Answer

EDMA Linux files for KeyStone devices are available from the following git locations:

https://git.ti.com/keystone-linux/uio-module-drv

https://git.ti.com/keystone-linux/uio-module-drv/trees/master

An example for the device tree that includes the EDMA definition is available in the Linux release /processorSDKLINUX_XX_XX_XX_XX/board-support/linux-4.4.12+gitAUTOINC+3639bea54a-g3639bea54a/arch/arm/dts/keystone.dtsi where processorSDKLINUX_XX_XX_XX_XX is the directory where the Linux release was installed. The code below was taken from the device tree.

udma0 {
compatible = "ti,keystone-udma";
};

uio_edma3: edma3 {
compatible = "ti,uio-module-drv";
mem = <0x02700000 0x000C0000>;
label = "edma3";
};

Q. What type of interrupts does the EDMA3 channel controller generate on transfer completion?

Answer:

There are two types of completion events that the EDMA3 generates:

• Intermediate Transfer Completion
• Complete Interrupt

Figure 2-2 of the EDMA3 Controller User Guide shows that a completion event can come from the transfer request process module and from one of the transfer controllers.

The first completion event is sent when a request is sent to the transfer controller. This event is called an intermediate transfer completion and it is enabled by bit 21 of the OPT word of the PaRam (ITCINTEN) for interrupt and by bit 23 (ITCCHEN) for chaining.

The complete interrupt comes from one of the transfer controllers and it is set when the transfer is complete. The complete interrupt is enabled by bit 20 (TCINTE) and bit 22 (TCCHE) of the OPT word of PaRam for generating interrupt and for chaining respectively.

When either events are enabled, the appropriate bit of the IPR/IPRH of the appropriate shadow register or the global register set registers is latched. The location of the bit that is set is defined by the TCC bits (bits 12-17) of the OPT word for the associated PaRam.

Transfer completion interrupts that are latched to the interrupt pending registers (IPR/IPRH) are cleared by writing a 1 to the corresponding bit in the interrupt pending clear register (ICR/ICRH).

Q. What type of events can initiate a DMA/QDMA transfer using EDMA3CC?

Answer:

There are multiple ways to initiate a programmed data transfer using the EDMA3 channel controller.

A DMA event can be initiated by three sources below:

• Event-Triggered Transfer Request: When an event is asserted from a peripheral or device pins, it gets latched in the corresponding bit of the event register (ER.En = 1). If the corresponding event in the event enable register (EER) is enabled (EER.En = 1), then the EDMA3CC prioritizes and queues the event in the appropriate event queue. When the event reaches the head of the queue, it is evaluated for submission as a transfer request to the transfer controller.

• Manually-Triggered Transfer Request: A manually-triggered DMA event is initiated by a write to the event set register (ESR) by the DSP/EDMA3. Writing a 1 to an event bit in the ESR results in the event being prioritized/queued in the appropriate event queue, regardless of the state of the EER.En bit. When the event reaches the head of the queue, it is evaluated for submission as a transfer request to the transfer controller.

• Chain-Triggered Transfer Request: A chain-triggered transfer event is triggered when the completion of one transfer automatically sets the event for another channel. When a chained completion code is detected, the value of which is dictated by the transfer completion code (TCC[5:0] in OPT of the PaRAM set associated with the channel), it results in the corresponding bit in the Chained Event Register (CER) being set (CER.E[TCC] = 1).

A QDMA event can be initiated by two sources below:

• Auto-triggered Transfer Request: A bit corresponding to a QDMA channel is set in the QDMA event register (QER) when a DSP/EDMA3 write occurs to a PaRAM address that is defined as a QDMA channel trigger word which is programmed in the QDMA channel mapping register (QCHMAP n) for the particular QDMA channel and the same channel is enabled via the QDMA Event Enable Register (QEER.En = 1).

• Link-Triggered Transfer Request: A bit corresponding to a QDMA channel is set in the QDMA Event Register (QER) when EDMA3CC performs a link update on a PaRAM set address that is configured as a QDMA channel matches QCHMAPn settings and the corresponding channel is enabled via the QDMA Event Rnable Register (QEER.En = 1).

Q. How does the DMAQNUM map a channel to a specific event queue in the EDMA3 channel controller?

Answer:

The DMA Channel Queue Number Register (DMAQNUMn) enables mapping of DMA channels and its associated events to any event queue in the EDMACC. There is a mapping between DMA channels and their corresponding bits in DMAQNUMn. See Table 4-7 of the EDMA Controller User Guide.

The above table provides the meaning of each value it holds in each DMA queue number DMAQNUM[n]. In addition, Section 4.2.1.5 and Table 4-6 of the EDMA Controller User Guide show the DMAQNUMn field descriptions.

When a particular DMA event En and its corresponding bit fields holds the value of "0", then the respective events are queued on DMA event queue number 0. Likewise, if it holds the value of "1", then the corresponding events are queued on queue number 1. Similarly, if it holds "2", events are queued on queue number 2 ... and so on.

Q. Why does an EDMA3 completion interrupt arrive early? Why would data be DMAed to memory late?

Answer:

TR packets from EDMA CC would typically be queued in the TC and would be serviced based on the priority mechanism. See the TCCMODE bit field of OPT and Table 2-3 in the EDMA Controller User Guide.

If TR is programmed for early completion, it should be quite normal since the data transfer is considered to be complete after the EDMACC submits a TR to the EDMATC. But the TC may still be transferring the data. In this mode, the channel controller would generate the TCC internally, which indicates the transfer is said to be complete but the actual data transfer would be still in progress.

Q. How do you ensure the DMA Transfer Completion Interrupt and the Interrupt Pending Register (IPR/IPRH) bit position is appropriate to the TCC value set upon transfer completion?

Answer:

The Channel Options Parameter (OPT) is the first 32-bit word of the PaRam. PaRam bit 21 ITCINTEN (Intermediate Transfer Completion Interrupt Enable) and bit 20 TCINTEN (Transfer Completion Interrupt Enable) control the interrupt generation upon queuing of the transfer (ITCINTEN) or the actual completion of the transfer (TCINTEN). If one of these bits is set, an event will be generated by the TC and is latched by a bit in the IPR/IPRH (Interrupt Registers and Interrupt Register High) registers. The IPR/IPRH set of two 32-bit registers supports up to 64 channels. The bit location of the channel interrupt in the IPR/IPRH register is determined by the value of the TCC (Transfer Complete Code). The TCC is in bits 12-17 of the OPT register (6 bits). Thus, it can address up to 64 locations.

EDMA3 controllers may use more than 64 channels (64 DMA channels and 8 QDMA channels). In that case, shadow registers must be use to accumulate more than 64 channels on IPR/IPRH set of registers.

Q. What is the difference between A-Sync and AB-Sync transfer modes in EDMA3?

Answer:

A-Sync and AB-Sync are used for 2D transfers and 3D transfers. There are two main differences between A-sync and AB-sync:

• The first is the trigger requirement. In A-sync mode, each transfer of 1D row of data should be triggered separately. In AB-sync mode, one trigger starts the transfer of all the 1D rows in the 2D matrix.
  

• The second difference has to do with the skip index of the source and the destination of the B dimension (SRCBIDX and DSTBIDX). In A-sync mode, the skip index is calculated from the last byte that was transferred in the previous 1D row. In AB-sync mode, the skip index is calculated from the start of the previous 1D row transfer.
  

More detailed information about the A-sync and the AB-sync is in Chapter 2.2.1 and 2.2.2 of the EDMA Controller User Guide.

Q. How do you evaluate the status of any pending completion requests from EDMA3CC, destination FIFO status, and error status on EDMA3TC?

Answer:

EDMA3CC Status Register (CCSTAT) provides information on the number of completion requests submitted to the transmit control (COMPACTV bits) and the activity of each one of the transfer queues (bits QUEACTV0, QUEACTV1, QUEACTV2, QUEACTV3).

Other indicators in the same register are the Channel Control Active (ACTV, bit 4), Write Status Active (WSTATACTV, bit 3), Transfer Request Active (TRACTV, bit 2), QDMA Event Active (QEVTACTV, bit 1) and DMA Event Active (EVTACTV, bit 0). See Table 4.25 in the EDMA3 Controller User Guide.

EDMA3TC Channel Status Register (TCSTAT) provides information on the destination FIFO (bits 4-6), write status active (bit 2), source active state (bit 1), and program status (bit 0). See Table 4.68 in the EDMA3 Controller User Guide.

Error indication is recorded in Error Register (ERRSTAT). See Section 4.3.4.2 and Section 4.3.4.1 of the EDMA3 Controller User Guide.

Q. What is the difference between Constant Addressing Mode (SAM/DAM=1) and Increment Mode (SAM/DAM=0)? Are there any limitations on buffer alignments between these two modes?

Answer:

The Constant Source Addressing Mode (SAM) or the Constant Destination Addressing Mode (DAM) are used when the DMA moves data to or from address that does not change. A typical case is hardware FIFO where the read and the write are always to and from the same locations. Other examples include peripherals where the ingress or egress data is written into a fixed memory mapped register.

The SAM (Source Address Mode; bit 0 in the OPT word of the PaRam) and DAM (Destination Address Mode; bit 1 in the OPT word of the PaRam) control the Constant Address Mode for the source address and the destination address respectively. If the SAM or DAM bit is set to 1, the corresponding source or destination address stays constant throughout the transfer.

Note that the number of bytes that are read or written for SAM/DAM=1 is defined in the FWID field (FIFO WIDTH; bit 10-8 in the OPT word of the PaRam)

Constant Addressing Mode is explained in detail in Section 2.3.8 of the EDMA Controller User Guide, which includes the following note:

Note: The Constant Addressing (CONST) mode has limited applicability. The EDMA3 should be configured for the CONST mode (SAM/DAM=1) only if the transfer source or destination (on-chip memory, off-chip memory controllers, slave peripherals) support the CONST mode. See the device-specific data manual and/or peripheral user's guide to verify if constant addressing mode is supported. If constant addressing mode is not supported, the similar logical transfer can be achieved using the increment (INCR) mode (SAM/DAM=0) by appropriately programming the count and indices values.

Q. What are shadow registers and how are they used?

Answer:

System on Chip (SOC) devices that have multiple processing cores need more control of EDMA execution to implement resource managing.

The EDMA3 Controller has eight sets of shadow registers. A set of shadow registers contains a set of (almost) all EDMA3 control registers. Each channel is associated with a set of shadow registers. When an EDMA3 channel transfers data, the registers that control the transfer are the registers in the shadow register set that is associated with the channel.

Table 2-7 of EDMA3 Controller User Guide describes the registers in a shadow register set. Registers DRAE (DMA Region Access Enable) and QRAE (QDMA Region Access Enable) define what channels are associated with what Shadow Registers. The name region is used because shadow registers determine what memory regions can be accessed by the channel that is associated with a specific shadow register.

Q. What is the EDMA3 linking feature and how do linking transfers happen?

Answer:

Linking is the feature of loading a new PaRam to a channel upon completion of the channel current transfer. Upon completion of a transfer, the transfer parameters are reloaded with new PaRam parameter set addressed by the 16-bit link address field of the current parameter set.

Linking only occurs when the STATIC bit (bit 3 of OPT word of the PaRam) is cleared to 0. That is, set is not static.

Note that even though a new PaRam is loaded into the channel, no new transfer starts until a there is a new trigger to the channel.

Q. What are channel chaining capabilities of EDMA3?

Answer:

The channel chaining capability for the EDMA3 allows the completion of an EDMA3 channel transfer to trigger another EDMA3 channel transfer. That is, after one EDMA channel completes, the second channel starts without CPU intervention. This feature enables the transfer of complex patterns with minimal intervention of CPU. The EDMA3 Controller User Guide describes chaining in Section 2.8.

Q. In what way do EDMA3 chained events differ from the EDMA3 linking feature when multiple events occur through receiving a single event?

Answer:

Linking works on PaRam:

• Linking loads a new PaRam to a channel after the transfer.
  

• Linking does not trigger the channel.
  

• Typical usage of linking is for ping-pong buffers, data buffers, or any fixed structure multiple buffers.
  

Chaining Works on channels:

• Chaining triggers a new channel when the current channel transfer completes.
  

• Typical usage of chaining is for complex data transfers that do not require CPU intervention.
  

Note: It is possible to have linking and chaining for the same transfer, even to the same channel. (That is, a new PaRam is loaded and the channel triggers itself)

The EDMA3 Controller User Guide describes Linking in Section 2.3.7 and Chaining in Section 2.8.

Q. Where are the EDMA3 LLD examples located in the LLD release?

Answer:

The Processor SDK RTOS release directory edma3_lld_X_XX_XX_XX has many example projects:

• In the CCS window edit perspective, click on the Project Tab and select import CCS Projects.
  

• A dialogue box will open. Navigate to the directory location of edma3 in the Processor SDK RTOS release.
  

• The window will contain about 70 projects (depending on the device release). The screen shot below shows the examples of EDMA3 for C66x Release 3.0.0.4 of Processor SDK RTOS:
  

• 

  EDMA3 Examples Projects

• Select one or more projects and click finish.
  

• Build the selected projects following instructions from the Processor SDK RTOS Developer Guide.

Q. What EDMA3 CSL examples are available in the Processor SDK RTOS release?

Answer:

EDMA3 CSL is part of the PDK module in the Processor SDK RTOS release. A test source code (and a make file in some of the devices) is in directory pdk_YY_X_XX_XX\packages\ti\csl\example\edma\edma_polled_mode_test where pdk_YY_X_XX_XX is the PDK module directory in the installed release.

Using CCS to build and run the CSL EDMA3 test requires starting a new CCS project and manually building the project.

Q. Where are the instructions on how to build and run the EDMA3 StarterWare examples that are available in the StarterWare releases?

Answer:

A detailed procedure is provided in the StarterWare Getting Started Wiki for building the Starterware libraries or applications on both Windows and Linux devices.

In order to run EDMA example applications with UART, I2C, and SPI peripherals in StarterWare releases, follow the steps mentioned in the Starterware User Guide Wiki, as well the individual Peripheral User Guide Wikis (with DMA mode of operation) shown here:

UART: http://processors.wiki.ti.com/index.php/StarterWare_UART

I2C: http://processors.wiki.ti.com/index.php/StarterWare_I2C

SPI: http://processors.wiki.ti.com/index.php/StarterWare_SPI

Q. Where are the instructions on how to build the Processor SDK and individual components from source that are available in the Processor SDK 2.0.1 release which includes Linux EDMA3 driver?

Answer:

Currently, the Processor SDK Linus perspective is available only for a Linux 64-bit computer. Processor SDK Linux Installer gives instructions how to download and install Linux releases for a variety of devices. Instructions how to set up the Linux build environment are part of the LINUX Startup Guide.

Processor SDK Linux Software Developer's Guide gives instructions for building all modules and peripheral code.

Instructions how to build the SDK and its examples can be found on the Processor SDK: Building The SDK Wiki.