Dual TMS320C6474 AMC Mezzanine board

Dual TMS320C6474 AMC Mezzanine board

The presence of AIF module in the embedded processor is primarily used for IQ stream data transfers between uplink and downlink baseband embedded processors and a high speed serial interface. The IQ sample width is formed of 15 or 16 bits for downlink data and 7 or 8 bits for uplink data with only a combination of 7/15 and 8/16 allowed. In this study case, the uplink/downlink data configuration is 16/8 bits.

The outbound data are sent to the CPRI™ – TDM FIC in order that I and Q data are sent simultaneously to the DAC. In this reception side, inbound data from the ADC are de-multiplexed by the CPRI™ – TDM FIC before reception in the embedded processor via CPRI link.

Embedded processor configuration for AIF module

Upon identification, CPRI link 0 from the CPRI™ - TDM platform is connected to CPRI link 5 of the embedded processor (Faraday 1):

In consequence, the AIF module should be programmed so that CPRI link 5 is activated. Below is the configuration visible in the constants.h:

<syntaxhighlight lang='c'> /*

 macros for:
 - changing link rate to 1x, 2x or 4x
 - choosing the appropriate link for data transfer
 - defining the outbound/inbound data/control word AIF RAM
 - defining the appropriate frame synchronization event generators

• /

1. define LINK_RATE 2
2. define CSL_AIF_LINK CSL_AIF_LINK_5
3. define AIF_INBOUND_CS_RAM_LINK AIF_INBOUND_CS_RAM_LINK_5
4. define AIF_INBOUND_CW_RAM_LINK AIF_INBOUND_CW_RAM_LINK_5
5. define AIF_OUTBOUND_CS_RAM_LINK AIF_OUTBOUND_CS_RAM_LINK_5
6. define AIF_OUTBOUND_CW_RAM_LINK AIF_OUTBOUND_CW_RAM_LINK_5
7. define CSL_FSYNC_TRIGGER_4_CHIPS CSL_FSYNC_TRIGGER_GEN_23

/*

  *	CSL_FSYNC_TRIGGER_4_CHIPS:
  *	CSL_FSYNC_TRIGGER_GEN_18	for link 0
  *	CSL_FSYNC_TRIGGER_GEN_19	for link 1
  *	CSL_FSYNC_TRIGGER_GEN_20	for link 2
  *	CSL_FSYNC_TRIGGER_GEN_21	for link 3
  *	CSL_FSYNC_TRIGGER_GEN_22	for link 4
  *	CSL_FSYNC_TRIGGER_GEN_23	for link 5

• /

1. define CSL_FSYNC_TRIGGER_38400_CHIPS CSL_FSYNC_TRIGGER_GEN_29

/*
  *	CSL_FSYNC_TRIGGER_38400_CHIPS:
  *	CSL_FSYNC_TRIGGER_GEN_24	for link 0
  *	CSL_FSYNC_TRIGGER_GEN_25	for link 1
  *	CSL_FSYNC_TRIGGER_GEN_26	for link 2
  *	CSL_FSYNC_TRIGGER_GEN_27	for link 3
  *	CSL_FSYNC_TRIGGER_GEN_28	for link 4
  *	CSL_FSYNC_TRIGGER_GEN_29	for link 5
  */

1. define INBOUND_RAM AIF_INBOUND_CS_RAM_LINK_5
2. define OUTBOUND_RAM AIF_OUTBOUND_CS_RAM_LINK_5

</syntaxhighlight>

Note: Make sure that the appropriate .gel file is loaded before running the program (idt_evmc6474.gel).