DM81xx NOR APPLICATION NOTES

1 Difference in the u-boot bootloader between NOR boot mode and other boot modes
2 NOR Device Pins
3 NOR Device initialization by ROM Boot loader
4 NOR u-boot start-up code
5 Information to be collected for interfacing NOR to DM81xx
6 Interfacing NOR Flash to DM816x
- 6.1 Interfacing DM816x with various daughter boards
  - 6.1.1 Interfacing with video application /catalog board
7 Interfacing NOR Flash to DM814x
- 7.1 Interfacing DM814x with various daughter boards
  - 7.1.1 Interfacing with catalog board
  - 7.1.2 Interfacing with video security board
8 Software Changes

Difference in the u-boot bootloader between NOR boot mode and other boot modes[edit]

1) u-boot min is not required. Since the NOR device is XIP, ROM Boot loader would directly execute the binary from NOR flash.

NON-XIP

In case of NON-XIP boot modes(nand, SPI, MMC/SD, UART), uboot image is first copied from the boot device to the SRAM and then only executed. Hence, the size of the first stage boot loader cannot exceed the SRAM size. In centaurus (TI814x), the size of the SRAM is 128 KB where as the u-boot size is more than 128 KB. So, the complete u-boot binary cannot be loaded into the SRAM. To acheive this, u-boot boot loader is divided into two stages. The first stage u- boot boot loader would only have the minimal features enabled so that it can be loaded into SRAM where as the u-boot second stage boot loader has all the features and is loaded by the first stage u-boot boot loader into DRAM.

XIP (NOR)

In case of XIP boot mode(NOR), ROM boot loader would directly execute from NOR. SRAM restriction does not apply and hence the complete u-boot binary can be flashed into the NOR device.

2) ROM boot loader does initialization to access only the first 4 KB of the NOR device. The U-Boot start up code has to configure the higher address lines to access the entire NOR device.

NOR Device Pins[edit]

NOR Flash uses the following pins/signals

GPMC_ADVN_ALE
GPMC_OEN_REN
GPMC BEN_CLE
GPMC_WEN
GPMC_WAIT
GPMC_CS
GPMC_CLK
GPMC_A0 to A27 [ Based on the NOR size]
GPMC_AD0 to AD15

NOR Device initialization by ROM Boot loader[edit]

In case of DM81xx NOR boot, ROM boot loader code would configure only the following pins

GPMC_ADVN_ALE
GPMC_OEN_REN
GPMC BE0N_CLE
GPMC_WEN
GPMC_WAIT
GPMC_CS0
GPMC_CLK
GPMC_A0 to A11
GPMC_AD0 to AD15

Higher address lines A12 to A27 are not configured by the NOR code. This puts limitation on the amount of memory accessible by the ROM Boot loader code. Since, only the lines A0-A11 are configured, ROM bootloader could address only the first 4 KB of NOR Device. Hence, the remaining lines have to be initalized by the u-boot boot loader software.

NOR u-boot start-up code[edit]

The NOR boot logic is handled in arch/arm/cpu/arm_cortexa8/ti81xx/lowlevel_init.S

Since ROM code does not initialize all 25 address lines required for accessing 64 MBytes, u-boot should first initialize GPMC to continue with the XIP beyond 4KBytes.
u-boot should also configure pin muxing for the remaining 13 address lines (gpmc_a12 - gpmc_a24) based on board schematics
In case of NOR boot and XIP, we cannot initialize GPMC while running from NOR, hence we have to relocate the tiny GPMC init code to SRAM and then transfer control to SRAM and then come back to NOR XIP.
Also, the relocatable GPMC init code should be placed in the first 4KBytes of the u-boot. This is achieved by adding lowlevel_init.o just below start.o in the u-boot linker script board/ti8168_evm/u-boot.lds as shown below.

SECTIONS
{
    . = 0x00000000;
    . = ALIGN(4);
    .text   :
    {
      arch/arm/cpu/arm_cortexa8/start.o  (.text)
      arch/arm/cpu/arm_cortexa8/ti81xx/lowlevel_init.o   (.text)
      *(.text)
    }
...
...
...

Before relocating any code to SRAM we have to first enable the SRAM.
All the above steps have to be done only if we are not already running from SRAM (or DDR)
*The diagram below explains the above discussed steps

Information to be collected for interfacing NOR to DM81xx[edit]

1. ROM Boot loader Booting document

2. DM81xx SOC Pin mux datasheet

3. DM81xx Base board schematics

4. NOR Daughter board schematics

It can be seen from the DM814x/DM816x pin mux sheet that NOR functionality is available on multiple pins. For e.g., address line A24 of NOR can be connected to any of the pad(gpmc_ben1, gpmc_cs2, mmc2_dat7) of DM814x. Depending on the daughter board, the NOR interface will vary. Hence, the pad control register has to be configured accordingly.

Interfacing NOR Flash to DM816x [edit]

DM816x NOR FUNCTION

Following table shows the various pins & modes in which the NOR functionality is available. This information can be obtained from the SOC(DM816x) pin mux sheet.

S.No	NOR Signal name	Muxed/Non-Muxed	Pad name	Mode
1	A0	Muxed	GPMC_A[0]	0
2	A1	Muxed	GPMC_A[1]	0
3	A2	Muxed	GPMC_A[2]	0
4	A3	Muxed	GPMC_A[3]	0
5	A4	Muxed	GPMC_A[4]	0
6	A5	Muxed	GPMC_A[5]	0
7	A6	Muxed	GPMC_A[6]	0
8	A7	Muxed	GPMC_A[7]	0
9	A8	Muxed	GPMC_A[8]	0
10	A9	Muxed	GPMC_A[9]	0
11	A10	Muxed	GPMC_A[10]	0
12	A11	Muxed	GPMC_A[11]	0
12	A12	Muxed	uart0_dtrn	2
			sc1_vppen	1
			tim7_out	1
			gpmc_cs5	1
14	A13	Muxed	mmc_clk	1
			uart1_ctsn	1
			sc1_data	1
15	A14	Muxed	mmc_pow	1
			uart1_rtsn	1
			sc1_clk	1
16	A15	Muxed	mmc_sdwp	1
			uart2_rtsn	1
			sc1_rst	1
17	A16	Muxed	mmc_sdcd	1
			uart2_ctsn	1
			sc1_det	1
18	A17	Muxed	SD_DAT[3]	1
			uart0_rin	1
			uart1_ctsn	2
19	A18	Muxed	SD_DAT[2]_SDRW	1
			uart0_dcdn	1
			uart1_rtsn	2
20	A19	Muxed	SD_DAT[1]_SDIRQ	1
			uart0_dsrn	1
			uart1_txd	2
21	A20	Muxed	SD_DAT[0]
			SD_DAT[0]	1
			uart0_dtrn	1
			uart1_rxd	2
22	A21	Muxed	mmc_cmd	1
			spi_scs3	1
			sc1_vccen	1
23	A22	Muxed	spi_scs2	1
			uart0_rin	2
			sc0_rst	1
24	A23	Muxed	spi_scs1	1
			uart0_dcdn	2
			sc0_vccen	1
			gp0_io6	2
25	A24	Muxed	uart0_dsrn	2
			sc0_vppen	1
			tim6_out	1
			gp0_io5	2
26	A25	Muxed	uart1_txd	1
			uart2_ctsn	2
			sc0_data	1
27	A26	Muxed	uart1_rxd	1
			uart2_rtsn	2
			sc0_clk	1
28	A27	Muxed	sc0_det	1
28	A27	Muxed	GPMC_A[27]	0
29	D0	Non-Muxed	gpmc_d0	0
30	D1	Non-Muxed	gpmc_d1	0
31	D2	Non-Muxed	gpmc_d2	0
32	D3	Non-Muxed	gpmc_d3	0
33	D4	Non-Muxed	gpmc_d4	0
34	D5	Non-Muxed	gpmc_d5	0
35	D6	Non-Muxed	gpmc_d6	0
36	D7	Non-Muxed	gpmc_d7	0
37	D8	Non-Muxed	gpmc_d8	0
38	D9	Non-Muxed	gpmc_d9	0
39	D10	Non-Muxed	gpmc_d10	0
40	D11	Non-Muxed	gpmc_d11	0
41	D12	Non-Muxed	gpmc_d12	0
42	D13	Non-Muxed	gpmc_d13	0
43	D14	Non-Muxed	gpmc_d14	0
44	D15	Non-Muxed	gpmc_d15	0
45	ADVN_ALE	Non-Muxed	gpmc_advn_ale	0
46	OEN_REN	Non-Muxed	gpmc_oen_ren	0
47	BE0N_CLE	Non-Muxed	gpmc_be0n_cle	0
48	WEN	Non-Muxed	gpmc_wen	0
49	WAIT	Non-Muxed	gpmc_wait	0
50	CS0	Non-Muxed	gpmc_cs0	0
51	CLK	Muxed	gpmc_clk	0

From the above table,

1. Following pins are used exclusively by NOR.

gpmc_d0-gpmc_d15
gpmc_advn_ale
gpmc_oen_ren
gpmc_be0n_cle
gpmc_wen
gpmc_wait
gpmc_cs0

2. Some of the NOR device functionalities are available on multple pins

. For. E.g.,Functionality of NOR signal A24 is available on the following pins

uart0_dsrn
sc0_vppen
tim6_out
gp0_io5

When interfacing to the NOR device , any of the above pins can be connected to the A24 signal of NOR Flash. User has to only ensure that the MODE field of the PAD control register for that Corresponding pin is configured for NOR functionaity.

Interfacing DM816x with various daughter boards[edit]

Interfacing with video application /catalog board[edit]

NOTE:

1. Since the NOR flash is 16 bit device, address line A0 is not used.

2. Since the NOR flash is 64 MByte, only the address lines a0-a25 are used. A26 and A27 are not used

3. A27 line is actually used as a GPIO pin to enable the higher address lines. It can be seen from the schematics(DM816x base board + catalog board) that A27 line is conencted to the gpio0-20 of DM816x.

4. Some of the NOR functionalities are available on multiple pins. The pins used by the NOR flash(catalogue board) in such cases are shown highlighted.

S.No	NOR Signal name	Muxed/Non-Muxed	Pad name	Mode
1	A0(Not used)	Muxed	GPMC_A[0]	0
2	A1	Muxed	GPMC_A[1]	0
3	A2	Muxed	GPMC_A[2]	0
4	A3	Muxed	GPMC_A[3]	0
5	A4	Muxed	GPMC_A[4]	0
6	A5	Muxed	GPMC_A[5]	0
7	A6	Muxed	GPMC_A[6]	0
8	A7	Muxed	GPMC_A[7]	0
9	A8	Muxed	GPMC_A[8]	0
10	A9	Muxed	GPMC_A[9]	0
11	A10	Muxed	GPMC_A[10]	0
12	A11	Muxed	GPMC_A[11]	0
12	A12	Muxed	uart0_dtrn	2
			sc1_vppen	1
			tim7_out	1
			gpmc_cs5	1
14	A13	Muxed	mmc_clk	1
			uart1_ctsn	1
			sc1_data	1
15	A14	Muxed	mmc_pow	1
			uart1_rtsn	1
			sc1_clk	1
16	A15, A15_1	Muxed	mmc_sdwp	1
			uart2_rtsn	1
			sc1_rst	1
17	A16	Muxed	mmc_sdcd	1
			uart2_ctsn	1
			sc1_det	1
18	A17	Muxed	SD_DAT[3]	1
			uart0_rin	1
			uart1_ctsn	2
19	A18	Muxed	SD_DAT[2]_SDRW	1
			uart0_dcdn	1
			uart1_rtsn	2
20	A19	Muxed	SD_DAT[1]_SDIRQ	1
			uart0_dsrn	1
			uart1_txd	2
21	A20	Muxed	SD_DAT[0]
			SD_DAT[0]	1
			uart0_dtrn	1
			uart1_rxd	2
22	A21	Muxed	mmc_cmd	1
			spi_scs3	1
			sc1_vccen	1
23	A22	Muxed	spi_scs2	1
			uart0_rin	2
			sc0_rst	1
24	A23	Muxed	spi_scs1	1
			uart0_dcdn	2
			sc0_vccen	1
			gp0_io6	2
25	A24	Muxed	uart0_dsrn	2
			sc0_vppen	1
			tim6_out	1
			gp0_io5	2
26	A25	Muxed	uart1_txd	1
			uart2_ctsn	2
			sc0_data	1
27	A26(NOT USED)	Muxed	uart1_rxd	1
			uart2_rtsn	2
			sc0_clk	1
28	A27(GPIO0 20)	Muxed	sc0_det	1
28	A27(GPIO0 20)	Muxed	GPMC_A[27]	1
29	D0	Non-Muxed	gpmc_d0	0
30	D1	Non-Muxed	gpmc_d1	0
31	D2	Non-Muxed	gpmc_d2	0
32	D3	Non-Muxed	gpmc_d3	0
33	D4	Non-Muxed	gpmc_d4	0
34	D5	Non-Muxed	gpmc_d5	0
35	D6	Non-Muxed	gpmc_d6	0
36	D7	Non-Muxed	gpmc_d7	0
37	D8	Non-Muxed	gpmc_d8	0
38	D9	Non-Muxed	gpmc_d9	0
39	D10	Non-Muxed	gpmc_d10	0
40	D11	Non-Muxed	gpmc_d11	0
41	D12	Non-Muxed	gpmc_d12	0
42	D13	Non-Muxed	gpmc_d13	0
43	D14	Non-Muxed	gpmc_d14	0
44	D15	Non-Muxed	gpmc_d15	0
45	ADVN_ALE	Non-Muxed	gpmc_advn_ale	0
46	OEN_REN	Non-Muxed	gpmc_oen_ren	0
47	BE0N_CLE	Non-Muxed	gpmc_be0n_cle	0
48	WEN	Non-Muxed	gpmc_wen	0
49	WAIT	Non-Muxed	gpmc_wait	0
50	CS0	Non-Muxed	gpmc_cs0	0
51	CLK	Muxed	gpmc_clk	0

Interfacing NOR Flash to DM814x[edit]

DM814x NOR FUNCTION

Following table shows the various pins & modes in which the NOR functionality is available. This information can be obtained from the SOC(DM814x) pin mux sheet.

S.No	NOR Signal name	Muxed/Non-Muxed	Pad name	Mode
1	A0 (Not used)	Muxed		1
2	A1	Muxed	mmc2_dat3	1
2	A1	Muxed	gmii0_rxd4	4
3	A2	Muxed	mmc2_dat2	1
3	A2	Muxed	gmii0_rxd5	4
4	A3	Muxed	mmc2_dat1	1
4	A3	Muxed	gmii0_rxd6	4
5	A4	Muxed	mmc2_dat0	1
5	A4	Muxed	gmii0_rxd7	4
6	A5	Muxed	vout1_g_y_yc1	4
6	A5	Muxed	gmii0_rxdv	4
7	A6	Muxed	vout1_g_y_yc0	4
7	A6	Muxed	gmii0_gtxclk	4
8	A7	Muxed	vout1_r_cr1	4
8	A7	Muxed	gmii0_txd0	4
9	A8	Muxed	vout1_r_cr0	4
9	A8	Muxed	gmii0_txd1	4
10	A9	Muxed	gmii0_txd2	4
10	A9	Muxed	vout1_b_cb_c1	4
11	A10	Muxed	gmii0_txd3	4
11	A10	Muxed	vout1_b_cb_c0	4
12	A11	Muxed	gmii0_txd4	4
12	A11	Muxed	vout1_fid	4
13	A12	Muxed	gmii0_txd5	4
13	A12	Muxed	vout0_fid	4
14	A13	Muxed	gmii0_txd6	4
14	A13	Muxed	vout1_g_y_yc2	1
15	A14	Muxed	gmii0_txd7	4
15	A14	Muxed	vout1_r_cr3	1
16	A15	Muxed	vout1_r_cr2	1
16	A15	Muxed	gmii0_txen	4
17	A16	Muxed	gpmc_a16	0
18	A17	Muxed	gpmc_a17	0
19	A18	Muxed	gpmc_a18	0
20	A19	Muxed	gpmc_a19	0
21	A20	Muxed	gpmc_a20	0
21	A20	Muxed	mmc2_dat7	2
22	A21	Muxed	gpmc_a21	0
22	A21	Muxed	mmc2_dat6	2
23	A22	Muxed	gpmc_a22	0
23	A22	Muxed	mmc2_dat5	2
24	A23	Muxed	gpmc_a23	0
24	A23	Muxed	mmc2_dat4	2
25	A24	Muxed	gpmc_ben1	1
			gpmc_cs2	1
			mmc2_dat7	1
26	A25	Muxed	gpmc_ben0	1
			gpmc_cs1	1
			mmc2_dat6	1
27	A26	Muxed	gmii0_rxd3	3
			gpmc_wait0	1
			mmc2_dat5	1
28	A27	Muxed	gmii0_rxd3	2
28	A27	Muxed	mmc2_dat4	1
29	D0	Non-Muxed	gpmc_ad0	0
30	D1	Non-Muxed	gpmc_ad1	0
31	D2	Non-Muxed	gpmc_ad2	0
32	D3	Non-Muxed	gpmc_ad3	0
33	D4	Non-Muxed	gpmc_ad4	0
34	D5	Non-Muxed	gpmc_ad5	0
35	D6	Non-Muxed	gpmc_ad6	0
36	D7	Non-Muxed	gpmc_ad7	0
37	D8	Non-Muxed	gpmc_ad8	0
38	D9	Non-Muxed	gpmc_ad9	0
39	D10	Non-Muxed	gpmc_ad10	0
40	D11	Non-Muxed	gpmc_ad11	0
41	D12	Non-Muxed	gpmc_ad12	0
42	D13	Non-Muxed	gpmc_ad13	0
43	D14	Non-Muxed	gpmc_ad14	0
44	D15	Non-Muxed	gpmc_ad15	0
45	ADVN_ALE	Muxed	gpmc_advn_ale	0
46	OEN_REN	Non-Muxed	gpmc_oen_ren	0
47	BE0N_CLE	Muxed	gpmc_ben0	0
48	WEN	Non-Muxed	gpmc_wen	0
49	WAIT	Muxed	gpmc_wait0	0
50	CS0	Muxed	gpmc_cs0	0
51	CLK	Muxed	gpmc_clk	0

From the above table,

1. Following pins are used exclusively by NOR.

gpmc_d0-gpmc_d15
gpmc_advn_ale
gpmc_oen_ren
gpmc_be0n_cle
gpmc_wen
gpmc_wait
gpmc_cs0

2. Some of the NOR device functionalities are available on multple pins

. For. E.g.,Functionality of NOR signal A24 is available on the following pins

gpmc_ben1
gpmc_cs2
mmc2_dat2

When interfacing the NOR flash, any of the above pins can be used as the A24 address line. User has to only ensure that the MODE field of the PAD control register for that Corresponding pin is configured for NOR functionaity.

Interfacing DM814x with various daughter boards[edit]

Interfacing with catalog board[edit]

NOTE:

1. Since the NOR flash is 16 bit, address line A0 is not used.

2. Since the NOR flash is 64 MByte, only the address lines a0-a25 are used. A26 and A27 are not used

3. A27 line is actually used as a GPIO pin to enable the higher address lines. As seen from the schematics(DM814x Base Board + Catalog Board), A27 is connected to the GPIO1-22 pin of DM814x.

4. Some of the NOR functionalities are available on multiple pins. The pins used by the NOR flash(catalogue board) in such cases are shown highlighted .

S.No	NOR Signal name	Muxed/Non-Muxed	Pad name	Mode
1	A0(Not used)	Muxed		1
2	A1	Muxed	mmc2_dat3	1
2	A1	Muxed	gmii0_rxd4	4
3	A2	Muxed	mmc2_dat2	1
3	A2	Muxed	gmii0_rxd5	4
4	A3	Muxed	mmc2_dat1	1
4	A3	Muxed	gmii0_rxd6	4
5	A4	Muxed	mmc2_dat0	1
5	A4	Muxed	gmii0_rxd7	4
6	A5	Muxed	vout1_g_y_yc1	4
6	A5	Muxed	gmii0_rxdv	4
7	A6	Muxed	vout1_g_y_yc0	4
7	A6	Muxed	gmii0_gtxclk	4
8	A7	Muxed	vout1_r_cr1	4
8	A7	Muxed	gmii0_txd0	4
9	A8	Muxed	vout1_r_cr0	4
9	A8	Muxed	gmii0_txd1	4
10	A9	Muxed	gmii0_txd2	4
10	A9	Muxed	vout1_b_cb_c1	4
11	A10	Muxed	gmii0_txd3	4
11	A10	Muxed	vout1_b_cb_c0	4
12	A11	Muxed	gmii0_txd4	4
12	A11	Muxed	vout1_fid	4
13	A12	Muxed	gmii0_txd5	4
13	A12	Muxed	vout0_fid	4
14	A13	Muxed	gmii0_txd6	4
14	A13	Muxed	vout1_g_y_yc2	1
15	A14	Muxed	gmii0_txd7	4
15	A14	Muxed	vout1_r_cr3	1
16	A15	Muxed	vout1_r_cr2	1
16	A15	Muxed	gmii0_txen	4
17	A16	Muxed	gpmc_a16	0
18	A17	Muxed	gpmc_a17	0
19	A18	Muxed	gpmc_a18	0
20	A19	Muxed	gpmc_a19	0
21	A20	Muxed	gpmc_a20	0
21	A20	Muxed	mmc2_dat7	2
22	A21	Muxed	gpmc_a21	0
22	A21	Muxed	mmc2_dat6	2
23	A22	Muxed	gpmc_a22	0
23	A22	Muxed	mmc2_dat5	2
24	A23	Muxed	gpmc_a23	0
24	A23	Muxed	mmc2_dat4	2
25	A24	Muxed	gpmc_ben1	1
			gpmc_cs2	1
			mmc2_dat7	1
26	A25	Muxed	gpmc_ben0	1
			gpmc_cs1	1
			mmc2_dat6	1
27	A26 (Not Used)	Muxed	gmii0_rxd3	3
			gpmc_wait0	1
			mmc2_dat5	1
28	A27(GPIO1-22)	Muxed	gmii0_rxd3	2
28	A27(GPIO1-22)	Muxed	mmc2_dat4	7
29	D0	Non-Muxed	gpmc_ad0	0
30	D1	Non-Muxed	gpmc_ad1	0
31	D2	Non-Muxed	gpmc_ad2	0
32	D3	Non-Muxed	gpmc_ad3	0
33	D4	Non-Muxed	gpmc_ad4	0
34	D5	Non-Muxed	gpmc_ad5	0
35	D6	Non-Muxed	gpmc_ad6	0
36	D7	Non-Muxed	gpmc_ad7	0
37	D8	Non-Muxed	gpmc_ad8	0
38	D9	Non-Muxed	gpmc_ad9	0
39	D10	Non-Muxed	gpmc_ad10	0
40	D11	Non-Muxed	gpmc_ad11	0
41	D12	Non-Muxed	gpmc_ad12	0
42	D13	Non-Muxed	gpmc_ad13	0
43	D14	Non-Muxed	gpmc_ad14	0
44	D15	Non-Muxed	gpmc_ad15	0
45	ADVN_ALE	Muxed	gpmc_advn_ale	0
46	OEN_REN	Non-Muxed	gpmc_oen_ren	0
47	BE0N_CLE	Muxed	gpmc_ben0	0
48	WEN	Non-Muxed	gpmc_wen	0
49	WAIT	Muxed	gpmc_wait0	0
50	CS0	Muxed	gpmc_cs0	0
51	CLK	Muxed	gpmc_clk	0

Interfacing with video security board[edit]

NOTE:

1. Since the NOR flash is 16 bit, address line A0 is not used.

2. Since the NOR flash used is only 64 MByte, only the address lines a0-a25 are used. A26 and A27 are not used

3. A27 line is actually used as a GPIO pin to enable the higher address lines. It can be seen from the schematics(DM814x Base board + Video Security board) that the A27 line is connected to the GPIO0- 25th pin.

4. Some of the NOR functionalities are available on multiple pins. The pins used by the NOR flash(catalogue board) in such cases are shown highlighted

S.No	NOR Signal name	Muxed/Non-Muxed	Pad name	Mode
1	A0(Not used)	Muxed		1
2	A1	Muxed	mmc2_dat3	1
2	A1	Muxed	gmii0_rxd4	4
3	A2	Muxed	mmc2_dat2	1
3	A2	Muxed	gmii0_rxd5	4
4	A3	Muxed	mmc2_dat1	1
4	A3	Muxed	gmii0_rxd6	4
5	A4	Muxed	mmc2_dat0	1
5	A4	Muxed	gmii0_rxd7	4
6	A5	Muxed	vout1_g_y_yc1	4
6	A5	Muxed	gmii0_rxdv	4
7	A6	Muxed	vout1_g_y_yc0	4
7	A6	Muxed	gmii0_gtxclk	4
8	A7	Muxed	vout1_r_cr1	4
8	A7	Muxed	gmii0_txd0	4
9	A8	Muxed	vout1_r_cr0	4
9	A8	Muxed	gmii0_txd1	4
10	A9	Muxed	gmii0_txd2	4
10	A9	Muxed	vout1_b_cb_c1	4
11	A10	Muxed	gmii0_txd3	4
11	A10	Muxed	vout1_b_cb_c0	4
12	A11	Muxed	gmii0_txd4	4
12	A11	Muxed	vout1_fid	4
13	A12	Muxed	gmii0_txd5	4
13	A12	Muxed	vout0_fid	4
14	A13	Muxed	gmii0_txd6	4
14	A13	Muxed	vout1_g_y_yc2	1
15	A14	Muxed	gmii0_txd7	4
15	A14	Muxed	vout1_r_cr3	1
16	A15	Muxed	vout1_r_cr2	1
16	A15	Muxed	gmii0_txen	4
16	A15_1	Muxed	uart0_rtsn	0
17	A16	Muxed	gpmc_a16	0
18	A17	Muxed	gpmc_a17	0
19	A18	Muxed	gpmc_a18	0
20	A19	Muxed	gpmc_a19	0
21	A20	Muxed	gpmc_a20	0
21	A20	Muxed	mmc2_dat7	2
22	A21	Muxed	gpmc_a21	0
22	A21	Muxed	mmc2_dat6	2
23	A22	Muxed	gpmc_a22	0
23	A22	Muxed	mmc2_dat5	2
24	A23	Muxed	gpmc_a23	0
24	A23	Muxed	mmc2_dat4	2
25	A24	Muxed	gpmc_ben1	1
			gpmc_cs2	1
			mmc2_dat7	1
26	A25	Muxed	gpmc_ben0	1
			gpmc_cs1	1
			mmc2_dat6	1
27	A26 (Not Used)	Muxed	gmii0_rxd3	3
			gpmc_wait0	1
			mmc2_dat5	1
28	A27(GPIO0-25)	Muxed	mca5_aclkx	7
29	D0	Non-Muxed	gpmc_ad0	0
30	D1	Non-Muxed	gpmc_ad1	0
31	D2	Non-Muxed	gpmc_ad2	0
32	D3	Non-Muxed	gpmc_ad3	0
33	D4	Non-Muxed	gpmc_ad4	0
34	D5	Non-Muxed	gpmc_ad5	0
35	D6	Non-Muxed	gpmc_ad6	0
36	D7	Non-Muxed	gpmc_ad7	0
37	D8	Non-Muxed	gpmc_ad8	0
38	D9	Non-Muxed	gpmc_ad9	0
39	D10	Non-Muxed	gpmc_ad10	0
40	D11	Non-Muxed	gpmc_ad11	0
41	D12	Non-Muxed	gpmc_ad12	0
42	D13	Non-Muxed	gpmc_ad13	0
43	D14	Non-Muxed	gpmc_ad14	0
44	D15	Non-Muxed	gpmc_ad15	0
45	ADVN_ALE	Muxed	gpmc_advn_ale	0
46	OEN_REN	Non-Muxed	gpmc_oen_ren	0
47	BE0N_CLE	Muxed	gpmc_ben0	0
48	WEN	Non-Muxed	gpmc_wen	0
49	WAIT	Muxed	gpmc_wait0	0
50	CS0	Muxed	gpmc_cs0	0
51	CLK	Muxed	gpmc_clk	0

Software Changes[edit]

Once the PAD control register values are obtained (As described above), following files have to be modified with this information.

DM814x Software changes

Flash Writer Source code

a) nor-flash-writer/src/device.c

The structure "nor_pad_cfg" contains pad configuration for catalog board. This has to be modified with the PAD control values for the respective daughter board

u-boot source code

a) arch/arm/cpu/arm_cortexa8/ti81xx/lowlevel_init.S

The address lines A12-A27[Line no 341-371of lowlevel_init.S ] have to be modified with PAD control values for the respective daughter board. By default, it is configured for catalog board

b) board/ti/ti8148/evm.c

The structure "nor_pad_cfg" contains pin mux configuration for catalog board. This has to be modified with PAD control values for the respective daughter board.

Linux

a) arch/arm/mach-omap2/devices.c

The function "ti814x_nor_init()" configures the pin mux for catalog board. This has to be modfied with PAD control values for the respective daughter board.

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DM81xx NOR APPLICATION NOTES

Contents

Difference in the u-boot bootloader between NOR boot mode and other boot modes[edit]

NOR Device Pins[edit]

NOR Device initialization by ROM Boot loader[edit]

NOR u-boot start-up code[edit]

Information to be collected for interfacing NOR to DM81xx[edit]

Interfacing NOR Flash to DM816x [edit]

Interfacing DM816x with various daughter boards[edit]

Interfacing with video application /catalog board[edit]

Interfacing NOR Flash to DM814x[edit]

Interfacing DM814x with various daughter boards[edit]

Interfacing with catalog board[edit]

Interfacing with video security board[edit]

Software Changes[edit]

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