DM816x C6A816x AM389x DDR3 Init Wordwise SWleveling

ReadMe First

The purpose of this document is to describe how to initialize DDR3 on all DM816x/C6A816x/AM389x devices using software leveling. The current approach uses static values for the software leveling process. Support for Asymmetric DDR2/3 memory interfaces is included.

Please refer to the attached presentation File:DDR3-Bring-up-Overview.pdf for an overview of the bring-up procedure.

The attached spreadsheet File:DM816x C6A816x AM389x EMIF4 Register Settings.zip can be used to calculate the DDR Register values based on the selected DDR SDRAM datasheet values.

Prerequisites

1. Excel spreadsheet for obtaining the seed values which is the input to the CCS based app File:RatioSeed.zip
2. CCS based program DDR3_slave_ratio_search.out which generates the static values for the software leveling process
3. TI816x U-Boot source code based on PSP release 04.00.00.07
4. U-Boot-DDR3.patch File:U-Boot-DDR3.zip for adding support for DDR3 in the U-Boot. This needs to be applied on top of the PSP release 04.00.00.07
5. Asymmetric-DDR3-memory-inteface.patch File:Asymmetric DDR3 interface.zip for adding support for Asymmetric DDR3 memory interface with PSP Release 04.00.00.13
6. U-Boot User Guide which is a part of the PSP release

Overview

In order to correctly setup DDR3 in these devices the approach used is software (slave ratio) leveling. The values to be used for software leveling are for specific board type and needs to be estimated using the CCS based program DDR3_slave_ratio_search.out which can be downloaded from here File:DDR3 slave ratio search.zip

The program DDR3_slave_ratio_search.out searches the window for the following Slave Ratio values on board based on the initial seed values to be keyed in on the command line(calculated based on DDR2/3 board topology), as explained in the next section.

1. Read DQS Slave Ratio
2. Read DQS Gate Slave Ratio
3. Write DQS Slave Ratio

Note that this program needs to be run for each new board type and for each operating frequency of DDR3.

Obtaining the seed values

The seed values for the ratios may be obtained using the File:RatioSeed.zip spreadsheet. The spreadsheet takes the following as inputs:

1. DDR3 clock frequency

2. Invert Clkout setting (Possible values: 0/1; Use 1 as the gel files are with this setting)

3. CK and DQS trace lengths in inches for each of the byte lanes.

The user inputs should be on these cells that are marked green. Once these fields are input, feed the values for B17, B18 and B19 for respective parameters to the CCS program.

Generating the static values

Hardware Setup

• Connect the JTAG emulator to the board using the JTAG ribbon cable and the 20/14 pin JTAG adapter (board specific).
• Connect the serial port output of the board to the serial port of the PC.
• Connect an Ethernet cable to the board with the other end connected to the local network.
• Make sure the Boot Mode / Configuration Select Switch are set to all 0s.

Starting CCS

• System Requirements – CCS 4.2.0.0700 or above installed on Windows XP with Service Pack 2
• Start CCSv4 by navigating to 'Start' menu in Windows XP
• Select the workspace folder where you want to store your project
• Use target configuration file ti816x.ccxml. If there is a need to crate a new configuration, then follow steps below
  • Select new Target Configuration "Target -> New Target Configuration"
  • Connection = TI XDS560 Emulator
  • Board or Device = TI816xEVM
  • Save configuration, e.g., ti816x.ccxml (On some CCS versions you might have to use the internal name of TI816x for this)
  • From next run, the project and target configuration will be readily available and can be skipped
• Select "Debug Perspective" in CCS if it is not there already: Window -> Open Perspective -> Debug
• Select View -> Target Configurations. Look for the target configuration ti816x.ccxml created in the previous step
• Right click and click "Launch Selected Configuration"
• This should launch debug session
• In Debug view select "TI XDS560 Emulator_0/Cortex A8" connection.
• Right click and select "Set Debug Scope" option. This will make remove all the cores except Cortex A8 from the debug view.
• Right click on the Cortex A8 core listed and click on "Connect Target"
• A "Disassembly" view with PC halted should pop up in one of the tabs. If not, issue a 'System Reset' from Target menu and then click on Halt

Loading GEL File

• Ensure that the GEL file Ti816x ddr.gel File:Ti816x ddr.zip is copied to the Windows Machine
• Select Tools -> GEL Files in CCS
• This opens a new tab in the Debug view. On right hand side empty area in this window, right click and use "Load GEL"
• Navigate to the directory containing gel file and select Ti816x ddr.gel.
• A "Scripts" menu item (on top) should now be available
• Select Scripts -> NETRA External Memory Initialization -> DDR3_xMHz_do_all()

Note: The GEL file has different menu options which to be used for different speeds of DDR3. 
Select the appropriate operating frequency in this step.

• This will perform system initialization and basic setup needed to load programs to the Cortex A8 core on the EVM.
• On success, you should see following at the CCS console:

     ....
     ....
     ....
     PRCM for OCMCRAM0/1 Initialization in Done  

• Note that sometimes the Scripts menu is disabled. In this case, go to Debug window and select "TI XDS560 Emulator_0/CortexA8 (top level node) and the Scripts menu should get activated.

Loading the CCS app

• At this point you will be in user mode on the A8 (marked as USR in the bottom right corner of CCS Status Bar). You will need to be in Supervisor (SPV) to run UBoot and the Linux Kernel. You can do that as follows:

1. View all Registers
2. Expand CPSR
3. Select “M” and set it to 0x13
4. These steps set the CPSR.M to 0x13 (SPV mode).

• Ensure that the CCS app <FIX ME> is copied to the Windows machine.
• Select Target --> Load program. Select the CCS program DDR3_slave_ratio_search.out for loading.

Running the app

• Select the CCS program DDR3_slave_ratio_search.out for loading.
• Select Target --> Run
• The program will prompt for the seed values. Enter the values estimated from the Excel spreadsheet.

The following shows an example run of the program

Enter 0 for EMIF0 & 1 for EMIF1
0 
DDR AADR=80000000

Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window
120

Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window
40

Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
80        

In the above example the seed values calculated based on the DDR3 board topology are entered.

Based on the seed value, the search window may or may not converge for the the slave ratios listed in Overview section.

For Asymmetric DDR2/3 memory interface (where trace lengths of DDR0 & DDR1 for CK & DQS are different), then DDR3_slave_ratio_search.out should be run twice to calculate the Slave Ratio values for DDR0(Memory Map Address =0x8000_0000) & DDR1(Memory Map Address=0xC000_0000).

For Symmetric DDR2/3 memory interface (where trace lengths of DDR0 & DDR1 for CK & DQS are almost equal or exactly equal), then DDR3_slave_ratio.search.out can be run for DDR0 interface only to calculate the Slave ratio values and the same slave ratio values can be used for DDR1 interface also.

Scenario A: It is applicable when the seed values calculated from the excel sheet are correct and all the slave ratios converge in a single run itself, as shown below.

Run 1:

Enter 0 for EMIF0 & 1 for EMIF1
0 
DDR AADR=80000000

Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window
120

Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window
40

Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
80
DLL Lock Values at Start  f0,  f3,  f3,  f3

===== Searching RD DQS GATE =====

RD DQS GATE RATIO MAX VALUE=1e0
RD DQS GATE RATIO MIN VALUE=dc
The RD DQS GATE OPTIMUM VAL=15e

===== Searching RD DQS =====

RD DQS RATIO MAX VALUE=6e
RD DQS RATIO MIN VALUE=c
The RD DQS OPTIMUM VAL=3d

===== Searching WR DQS =====

WR DQS RATIO MAX VALUE=e4
WR DQS RATIO MIN VALUE=a
The WR DQS RATIO OPTIMUM VAL=77

===== END OF TEST =====

All slave ratios converges in Run 1. You may choose to run it one more time to be sure that the converged "optimum values" are same. However, there can be small variations across different run based on the voltage and temperature on the board. In that case you can choose to enter converged values from either run 1 or run 2.

Key-in the optimum values for Run 2

Run 2:

Enter 0 for EMIF0 & 1 for EMIF1
0 
DDR AADR=80000000

Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window
15e

Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window
3d

Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
77
DLL Lock Values at Start  ef,  f3,  f3,  f3

===== Searching RD DQS GATE =====

RD DQS GATE RATIO MAX VALUE=1e0
RD DQS GATE RATIO MIN VALUE=d8
The RD DQS GATE OPTIMUM VAL=15c

===== Searching RD DQS =====

RD DQS RATIO MAX VALUE=6d
RD DQS RATIO MIN VALUE=b
The RD DQS OPTIMUM VAL=3c

===== Searching WR DQS =====

WR DQS RATIO MAX VALUE=e5
WR DQS RATIO MIN VALUE=9
The WR DQS RATIO OPTIMUM VAL=77

===== END OF TEST =====

If you compare Run 1 and Run 2 results the search values for the slave ratios are almost same. Note down the Optimum value for each slave ratio and enter either in the GEL file or the U-Boot code as described below.

Scenario B : It is applicable when the seed values calculated from the excel sheet don't help converge all the slave ratios in a single run. The example below shows that DQS Slave Ratio Converges but other slave ratios do not. In this case the values which have converged needs to be used iteratively until all three values converge.

Run 1:

Enter 0 for EMIF0 & 1 for EMIF1
0 
DDR AADR=80000000

Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window
80                                                                              
                                                                            
Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window    
40                                                                              

Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
80                                                                              

DLL Lock Values at Start  f0,  f3,  f3,  f3                                     

===== Searching RD DQS GATE =====
                                                     
RD DQS GATE RATIO MAX VALUE=1d4                                               
RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
The RD DQS GATE OPTIMUM VAL=ea                                 
                                                         
===== Searching RD DQS =====                                                     

RD DQS RATIO MAXIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE

===== Searching WR DQS =====
                                 
WR DQS RATIO MAXIMUM VALUE DIDN'T CONVERGE
WR DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
                                                               
===== END OF TEST =====                                 
       

In Run 1, all the slave ratios did not converged. Re-run the program and key-in the converged value to program, to search the window.

Run 2: 

Enter 0 for EMIF0 & 1 for EMIF1
0 
DDR AADR=80000000

Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window

ea --> This value has converged above and used in this iteration instead of earlier value.

Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window    
40
 
Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
80
DLL Lock Values at Start  ef,  f3,  f3,  f3
                                            
===== Searching RD DQS GATE =====                                                

RD DQS GATE RATIO MAX VALUE=1e0
RD DQS GATE RATIO MIN VALUE=dc
The RD DQS GATE OPTIMUM VAL=15e

===== Searching RD DQS =====

RD DQS RATIO MAX VALUE=50
RD DQS RATIO MIN VALUE=c
The RD DQS OPTIMUM VAL=2e

===== Searching WR DQS =====

WR DQS RATIO MAX VALUE=e4
WR DQS RATIO MIN VALUE=8
The WR DQS RATIO OPTIMUM VAL=76

===== END OF TEST =====
       

In Run 2, all the values converged. If all the three values would not have converged, run 1 more search and key-in the Run 2 seed values for Run 3

Run 3:

Enter 0 for EMIF0 & 1 for EMIF1
0 
DDR AADR=80000000

Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window
15E 

Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window
2e

Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
76
DLL Lock Values at Start  ef,  f3,  f3,  f3

===== Searching RD DQS GATE =====

RD DQS GATE RATIO MAX VALUE=1e0
RD DQS GATE RATIO MIN VALUE=c8
The RD DQS GATE OPTIMUM VAL=154

===== Searching RD DQS =====

RD DQS RATIO MAX VALUE=6e
RD DQS RATIO MIN VALUE=c
The RD DQS OPTIMUM VAL=3d

===== Seaching WR DQS =====

WR DQS RATIO MAX VALUE=e4
WR DQS RATIO MIN VALUE=8
The WR DQS RATIO OPTIMUM VAL=76

===== END OF TEST =====

If you compare Run 2 and Run 3 results the search values for the slave ratios are almost same. Note down the Optimum value for each slave ratio and enter either in the GEL file or the U-Boot code as described below.

Reset the Board or Issue POR. Repeat the steps for searching for the slave ratios for different DDR2/3 frequencies.

Modifying U-Boot

The values generated in the previous step are used in U-Boot (with the File:U-Boot-DDR3.zip patch applied) for the software leveling process. While plugging in the values in U-Boot please ensure that the changes are done for the same clock speed for which the program was executed in the previous step.

• Open the file arch/arm/include/asm/arch-ti81xx/ddr_defs.h. For EZSDK 5.0.0.56 this is psp/u-boot-2010.06-psp04.00.00.07/arch/arm/include/asm/arch-ti81xx/ddr_defs.h
• At the top of the file add the #defines shown below as appropriate

[...]
#ifdef CONFIG_TI816X_EVM_DDR3

#define CONFIG_TI816X_DDR3_400 /* Values supported 400,531,675,796 */
#define CONFIG_TI816X_DDR3_SW_LEVELING /* Enable software leveling as part of DDR3 init */
[...]

• The values obtained in the previous step need to be plugged under the appropriate #define

Eg: For DDR3-800 (I/O Bus Clock of 400MHz)
[...]
#if defined(CONFIG_TI816X_DDR3_400)
/* For 400 MHz */
#define EMIF_TIM1    0x0CCCE524
#define EMIF_TIM2    0x30308023
#define EMIF_TIM3    0x009F82CF
#define EMIF_SDREF   0x10000C30
#define EMIF_SDCFG   0x62A41032
#define EMIF_PHYCFG  0x0000030B

#if defined(CONFIG_TI816X_DDR3_SW_LEVELING)
/* These values are obtained from the CCS app */
#define RD_DQS_GATE     0x154 --> obtained in the previous section
#define RD_DQS          0x3D
#define WR_DQS          0x76
#endif

#endif  /* CONFIG_TI816X_DDR3_400 */
[...]

Note that the values used here are for representative purposes only. Use the values obtained from the CCS program over here

• Open the file arch/arm/include/asm/arch-ti81xx/clocks_ti816x.h which is in /psp/u-boot-2010.06-psp04.00.00.07/ in EZSDK 5.0.0.56 and add the #define shown below as appropriate

#define DDR_PLL_796     /* Values supported 400,531,675,796 */

• Open the file include/configs/ti8168_evm.h, for EZSDK 5.0.0.56 this is psp/u-boot-2010.06-psp04.00.00.07/include/configs/ti8168_evm.hand make sure the following changes are there

[...]
#define CONFIG_TI816X_EVM_DDR3                  /* Configure DDR3 in U-Boot */
//#define CONFIG_TI816X_EVM_DDR2                /* Configure DDR2 in U-Boot */
[...]

• Rebuild and flash U-Boot as described in the U-Boot user guide.

Run mtest

Simple memory test can be run from the U-Boot prompt using the mtest command. The syntax of the command mtest command is given below:

 mtest <start-address> <end-address> <test pattern> <# of iterations>

This command incrementally writes the test pattern to the memory range specified and then reads it back. Running the memory test with a few patterns should be sufficient for checking out the memory.

Run the memory test over the DDR address space of the EMIFs one by one:

 TI8168_EVM# mtest 0x80000000 0xA0000000 0xaa55aa55 3 (referred as Test A)
 TI8168_EVM# mtest 0xA0000000 0xC0000000 0xaa55aa55 3 (referred as Test B)

You can try different patterns (say all 0s, then all Fs and so on) to be sure of the memory reliability.

Interpreting the mtest result

• Test A and Test B both pass consistently - Memory corruption can be ruled out
• Test A passes but Test B fails - Only 512MB can be used if needed. The memory part needs to be changed
• Test A fails but Test B passes - Only 512MB can be used if needed. The memory part needs to be changed
• Test A and Test B both fail - The setup cannot be used. The memory part needs to be changed.