DM816x AM389x PCIe Clocking Schemes

		Wiki Note
DM816x AM389x PCIe Clocking Schemes
Author(s):Hemant Pedanekar		Texas Instruments
SPRWIKI9572		November 2012
Abstract
This application note describes various clocking schemes that could be used for designating source of reference clock (refclk) used for PCI Express (PCIe) systems consisting DM816x DaVinci/ AM389x Sitara family of devices.

OVERVIEW

DM816x/AM389x devices have PCI Express hardware module which can either be configured to act as a Root Complex (RC) or a PCIe Endpoint (EP). In either modes, it requires a 100MHz reference clock to drive the PHY and internal PLL. Depending upon the mode of operation, different schemes are possible to decide the source of the refclk.

For the rest of this document, we will refer DM816x and AM389x devices as DM816x since the PCI Express hardware is same on them.

This document considers following setup to describe the clocking schemes for refclk:

• DM816x Evaluation Board (EVM)
• PCIe x4 Male-Male cable to connect the x4 slot on EVM to peer board's slot when using board-board setup where both the boards have PCIe slots (at least x4)
• A PCIe EP card (e.g., an Ethernet Controller card) which can be connected to DM816x EVM used as RC

Note: Though this document uses DM816x EVM for reference, most of the details covered will also be applicable when using any other custom board having DM816x/AM389x device provided they have at least x1 PCI Express slot.

PCIe Refclk Considerations

This section covers the background for deciding refclk schemes to be used.

Refclk Architectures

As per the PCI Express Base Specification (v2.0), following refclk architectures are possible:

• Common Refclk
• Separate (independent) Refclks
• Data driving PLL

For the scope if this document, we will consider common refclk and independent refclk schemes.

Clocking Constraints

The spec further imposes following constraints on clocking:

• Refclks tolerance on peers should be within +- 300ppm
• If Spread Spectrum Clocking (SSC) is desired, the modulation frequency should be between 30KHz to 33KHz with modulation amplitude within 0% to -0.5% limit (-5000ppm, down-spread)
  • Since the modulated clocks still need to obey 600ppm limit, generally common refclk mechanism needs to be used across peers when one node (RC) is using SSC.

NOTE: For a proper functioning system, it is mandatory that the refclk constraints mentioned above are always met.

Refclk Schemes on DM816x EVM

The DM816x EVM has 100MHz fixed refclk generator providing two differential pairs as output - one pair sources DM816x refclk while the other pair is routed to on board PCIe slot pins A13 and A14.

Following subsections describe various refclk schemes recommended to be used with DM816x depending upon the mode of operation and setup.

DM816x as Root Complex

This section describes the schemes that can be used for routing refclk when DM816x device is set up as RC.

Refclk Sourced from DM816x EVM

In this mode, the 100MHz refclk output on PCIe slot on EVM acts as the refclk source to the connected EP device. This is the normal scenario when connecting a PCI Express card to the EVM, e.g., and x1 PCIe Gigabit Ethernet card connected in x4 slot on EVM. Most of the cases, the PCIe card will use the refclk from A13-A14 pins on the PCIe slot.

Independent Clocks

In some cases, an EP may use local source for refclk rather than using the refclk from PCIe slot. For example, when using another DM816x EVM as EP and/or using a PCIe Male-Male cable which doesn't have A13-A14 pins connected across both ends.

DM816x as Endpoint

This section describes the schemes that can be used for routing refclk when DM816x device is set up as EP.

Independent Clocks

DM816x EVM does not use the refclk from PCIe slot, instead the on board 100MHz fixed refclk is used which will result in the upstream device (e..g, RC or a PCIe Switch) and Dm816x device using independent refclks.

This should not create issues as long as the upstream uses fixed refclk and the +-300ppm tolerance constraint is not violated.

Refclk Sourced from PCIe Connector

NOTE: If the upstream uses SSC, it is required to use the same clock as reclk sourced from PCIe slot as input to DM816x EP.

In this mode, the refclk sourced from the upstream (e.g., a PC used as RC) is received on the PCIe slot (A13-A14 pins) on EVM and fed to DM816x.

This requires modifications on the EVM and PCIe cable as described below.

EVM Modifications

CAUTION: After the modifications mentioned below, the EVM can no longer be used for RC mode of operation^*.

^*May still be possible if you are using an unmodified DM816x EVM as EP and PCIe cable modified to connect A13 and A14 pins across both ends.

Since by default the EVM cannot receive refclk from the PCIe slot and instead uses on board refclk generator, we need to do following modification to enable using refclk received from PCIe slot.

• Remove the clock generator CDCM61002 (labeled as U30 on EVM). This component is located near the PCIe slot and SATA port (circled in red in picture below).

• Short the tracks on EVM which go to pin 3 and pin 6 of U30
• Short the tracks on EVM which go to pin 2 and pin 5 of U30
  • Note that all these pins are on the side towards PCIe slot
  • See picture below with U30 removed and tracks shorted

PCIe Cable Modifications

This modification is required to ensure that the refclk from the PCIe slot on RC reaches the PCIe slot in EVM and required if the pins A13 and A14 on one end on PCIe cable are not connected to respective pins on other end.

• Use a wire to connect the track which goes to A13 of PCIe slot on one end to A13 on the other end
• Similarly, connect A14 on one end to A14 on the other end

Note that these wires will carry 100MHz clock.

Alternatively, you can get a custom or commercially available cable which ensures signal mappings as shown below.