DA8xx PA/F Audio Data formats

Overview

The audio format for DA8xx performance audio framework is always two 32 bit channesl per IO pin:

Audio format - 2 channels per I/O pin

Bellow there are explanations clocks, rates and McASP specific details.

Master Clock

The Master clock is the high frequency system clock from which all other bit clocks and frame sync clocks are derived. This is usually generated externally because of the flexibility needed. From the master clock usually it is necessary to generate multiples of 44.1 KHz as well as multiples of 48 KHz, only with integer dividers. An external source can provide that flexibility.

From page 25 of the TMS320C674x/OMAP-L1x Processor Multichannel Audio Serial Port (McASP) User's Guide, the master clock is an input to the AHCLKX pin:

Frame Sync Generator Block Diagram - Master clock

The clock divider needs to be set to generate bit clock from the MCLK.

• aka: mclk, ahclkx, ahclkr
• Typically 128*fs, 256*fs, or 512*fs

Bit rate

The bit rate is generated by dividing the master clock, and it si always considering the audio format to be two 32 bit channels per IO pin. It should always be 64*fs for PA/F.

From the bit clock, according to the McASP register configurations, frame sysnc is generated. Page 27 of the TMS320C674x/OMAP-L1x Processor Multichannel Audio Serial Port (McASP) User's Guide shows bit clock in the ane Sync Generator Block Diagram:

Frame Sync Generator Block Diagram - bit clock

• aka: bclk, sclk, aclkx, aclkr

Sampling Frequency

The samplimg frequency is the rate at which one stereo I2S frame (64 bits) is transferred. Frame sysnc is generated from the bit clock according to the McASP register configurations. Please see page 27 the TMS320C674x/OMAP-L1x Processor Multichannel Audio Serial Port (McASP) User's Guide:

Frame Sync Generator Block Diagram - Frame rate

• aka: lrclk, fsclk, fs, afsx, afsr
• CD: fs=44.1kHz, DVD: fs=48kHz

Formulas

As explained above, the bit clock is generated from the MCLK using the output divider:

BCLK =  MCLK _
       Divider

So if a different FS is desired (that is generated from bit clock), than the clock divider should change. The software implementation for this is at dap_e17.c or dap_cus.c files.

The sampling rate (FS) is always configured in the McASP registers to be:

FS = Bit clock --> due to the stereo I2S frame (64 bits) format
        64

For example, is you have a Master clock of 24MHz (24,576,000 Hz) and you want a frame rate of 48KHz:

Bit clock = 48 KHz * 64 = 3072000

To calculate the divider needed:

Divider = MCLK/BCLK = 24,576,000 / 3,072,000 = 8