DA8xx Hardware design

Introduction

This page describes basic concept & information about Hardware design for DA8xx SDK.

• Target reader of this page is person who designs his own hardware platform for PA/F SDK. Not for just software developer.
• Usually information of this page is needed when starts hardware concept design.

H/W design

Boot mode selection pin settings

There are several selection for DSP boot, but most basic one is the SPI serial Flash. There are two options for SPI serial Flash Boot as below:

Boot Modes selction

	BOOT[7]	BOOT[2]	BOOT[1]	BOOT[0]	BOOT[3]
SPI0 Flash	0	1	0	1	X
SPI1 Flash	0	1	1	0	X

• BOOT[7] pin is multiplexed with SPI1_CLK//EQEP1S//GP5[7]
• BOOT[2] pin is multiplexed with SPI0_CLK//EQEP1I//GP5[2]
• BOOT[1] pin is multiplexed with SPI0_SIMO[0]//EQEP0S//GP5[1]
• BOOT[0] pin is multiplexed with SPI0_SOMI[0]//EQEP0I//GP5[0]

Above configuration may change in future. To confirm latest configuration, see this latest document.

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Connection to boot device (spi flash)

SPI serial Flash boot is the most common boot up option in DA8xx. As below, you can select both SPI0 or SPI1 to connect boot serial Flash ROM device.

connection between DSP & Serial SPI

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SDRAM connection

There is several options on SDRAM selection, such as number of Banks, num of Address bit and so on. Below are exemple of some typical SDRAM selection and connection for them.

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Audio i/o connection & clocking scheme

I- topology

Below are example of some typical Audio Clock connection for I-topology System.

• In case Input Slave, Output Master with Master clock(AHCLKX) provided

• In case Input Slave, Output also Slave

• In case Input Master, Output also Master

Y- topology

Below are example of some typical Audio Clock connection for Y-topology System. In Y-topology, there are 2 output zone, primary output & 2ndary output.

Primary output & 2ndary output are needed to synchronize each other, even though it is acceptable to double rate or quadrature rate. So the output clock source have to be shared in any place.

• In case 2ndary output is DIT. This is very simple because additional output is just 1 pin.

• In case 2ndary output is not DIT. This case, output is not limited as 2ch, likely to DIT.

Z- topology

Below is an example of the typical Audio Clock connection for Z-topology System. In Z-topology, there are 2 input zone and also 2 output zone. Those 2 inputs have to be synchronized, so the clock source have to be shared in any places. Of course, 2 output zone have to be synchronized, as Y-topology.

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Control communication

There are 2 option for the DSP & host Micro command communication, SPI & I2C.

SPI

• 5pin SPI

TI strongly recommends 5 pin connection which includes standard 4 SPI pins & "ENA",which is something like "Ready pin" of the DSP communication.
Usually, General purpose I/O on the HOST Micro will be connected with pull-up register.

And actually, when both SPI Serial Flash & Host micro are connected to DSP, each one should be separate SPI port, such as HOST Micto is "0", and Serial Flash is "1". Opposite selection is also available.

I2C

Simply connect I2C pins. Both 0 & 1 are available.