DA8xx Customization of Custom System Stream

Introduction

Custom System Stream 0 (CSS0) is not supplied as part of PA SDK, you need to download sample files and add them to your project. This section describes how to add example custom system stream. What is custom system stream is described in DA8xx UG. Please refer before stating this section. You can make your custom ccs0 by editing files explained below procedure.

Procedure

1. Change pa.cfg as follows.

   IDL_dap = bios.IDL.create("IDL_dap");

   IDL_dap.fxn = "DAP_watchDog";

   IDL_as1 = bios.IDL.create("IDL_as1");

   IDL_as1.fxn = "audioStream1Idle";

   /*Add following for css0*/

   IDL_css0 = bios.IDL.create("IDL_css0");

   IDL_css0.fxn = "customSystemStream";

2. Add the file css0.c to the project. If this step is omitted, the linkage created in the previous step will cause a build error. This file has the actual processing function of this example customSystemStreamIdle.
3. Select the desired build configuration, and build the project. A successful build should result without any errors.
4. Add the alpha code symbol definition file css0_a.h either to (1) the PA SDK Master Alpha Code Symbol Definition File (e.g., y13_a.h), or to (2) the calfa command line using the option -icss0_a.h. If this step is omitted, alpha code queries as from css0_a.h will produce errors.

Custom System Stream 0 (CSS0) provides the following features

• Three 8-bit registers are provided: Mode, Diff, and Copy.

• The default Mode is 3, which enables difference computation (Mode&1) as well as difference copy (Mode&2) as described below .

• Difference computation causes the numerical difference in register values, but not in Hz, to be computed between the Output Buffer Sample Rate and the Input Buffer Sample Rate Status Registers and stored in the CSS0 Diff Select Register.

• Difference computation is enabled if the CSS0 Mode Control Register bit 0 is set, and it is disabled otherwise. In the latter case, this register can be read or written with arbitrary values. In the former case, this register can be read, but any value written will be overwritten by the difference computation.

• Difference copy causes the CSS0 Diff Select Register to be copied to the CSS0 Copy Select Register. Difference copy is enabled if the CSS0 Mode Control Register bit 1 is set, and it is disabled otherwise. In the latter case, this register can be read or written with arbitrary values. In the former case, this register can be read, but any value written will be overwritten by the difference computation.

Behavior of Simple Custom System Stream

• The hehavior described in "Custom System Stream 0" above can be illustrated as follows:

-Source DTS (DVD) material to produce 48 kHz output.
 The query readCCSCopy will yield the result 0xfa03,0x0600 in which the least significant
 byte of the second word is interpreted as the value of the CCS0 Copy Select Register:
 0. This value indicates that the input and output sample rates are identical.

-Source DTS 96/24 (DVD) material to produce 96 kHz output.
 The query readCCSCopy will yield the result 0xfa03,0x0602 in which the least significant
 byte of the second word is interpreted as the value of the CCS0 Copy Select Register:
 2. This value indicates that the relationship between the input and output sample
 rates is 48 kHz to 96 kHz.

-Attempt to set the CCS0 Copy Select Register to 1 using writeCCSCopyN(1). Wait.
 The query readCCSCopy will yield the result 0xfa03,0x0602. The attempt to set this
 register value has “failed” because the Custom System Stream manipulates this register,
 overwriting any value set externally.

-Set the CCS0 Mode Control Register to disable update of the Copy Select Register
 using writeCCSModeEnableDiffOnly. Wait. Now, attempt to set the CCS0 Copy Select
 Register to 1 using writeCCSCopyN(1). Wait.
 The query readCCSCopy will yield the result 0xfa03,0x0601. The attempt to set this
 register value has “succeeded” because the Custom System Stream does not manipulate
 the value of this register.

• Note the need to “wait” in the examples above—this can be as simple as the use of separate alpha code sequences with calfa. This is required to allow operation of the Custom System Stream so that transitory register values “settle out” before subsequent operations that depend upon these register values are engaged. The following are suggested exercises for the reader.

-Return to system defaults. Source DTS (DVD) material to produce 48 kHz output.
 Separate alpha code sequences writeCCSCopyN(1) and readCCSCopy will yield the
 result that the CCS0 Copy Select Register value is 0. The combined alpha code
 sequence writeCCSCopyN(1),readCCSCopy will likely yield the result that the CCS0
 Copy Select Register value is 1.
 If such operations are not to be typical in the use of Custom System Stream 0, a restriction
 to “wait” is reasonable. If such operations would be typical, however, a restriction
 to “wait” would be onerous.
 Better design of the Custom System Stream to disable interrupts, as appropriate but not
 excessively, could remove the need for such a restriction. Such design is suggested as
 an exercise for the reader.

-Return to system defaults. Source DTS (DVD) material to produce 48 kHz output.
 Consider the “wait” required between the operations writeCCSModeEnableDiffOnly,
 writeCCSCopyN(1), and readCCSCopy described in the example above. Similar considerations
 as in the first exercise above apply here as well.