DA8xx Control Communication Customization

Introduction

This page describes methods needed to customize standard PA software for control communication for dsp-only applications. The standard PA SDK deliverable provides support for reference hardware DA8xx EVM. PA/F can be customized to execute on custom H/W. For control communication DCS6 has support for dmax and non-dmax level Processing for SPI,I2C and UART communicaton. But note that dmax level processing for read and write alpha commands should not be used with this SDK

Customizing DCS6

DCS6 module provides the ability to control the PA software running on the DA8xx DSP and also obtain status information about the PA system. DCS6 module provides configurability via parameterization in dcs6_params.c and dcs6_params.h implementation files. The DCS6 module provides configurability in two forms namely common parameters and device specific parameters. Details on all supported configurations and options available through dcs6 is available in dcs6 documentation in {SDK_INSTALL_DIR}\pa\doc\dcs6.html. In this document we only deal with important customizations required in DCS6 for use in custom hardware. Required customizations in dcs6_params.c to use DCS6 on custom hardware are listed below:

Modify DCS6_PARAMS

The DCS6 module provides the system integrator the ability to control the DCS6 behavior via the DCS6_Params structure:

typedef struct DCS6_Params{
   Uint32 size;    /* size of the structure */
   Uint8 dev;      /* device */
   Uint8 psfil;    /* process zero-fill (dMAX,DSP) */
   Uint8 pslc;     /* process serial link control (dMAX,DSP) */
   Uint8 pr;       /* process type 2,3,4 read alpha commands (dMAX,DSP) */
   Uint8 pw;       /* process type 2,3,4 write alpha commands (dMAX,DSP) */
   Uint8 edr;      /* error detection and reporting */
   Uint8 res[2];   /* reserved */
   Uint16 rxSize;  /* receive buffer size */
   Uint16 rxHwm;   /* receive buffer high watermark */
   Uint16 rxLwm;   /* receive buffer low watermark */
   Uint16 txSize;  /* transmit buffer size */
   DCS6_Params_Dev *pDev;    /* device parameters */
}DCS6_Params;

Details on all the different parameters and supported options are available in DCS6 documentation.In the following documentation, the default settings in SDK for EVM are highlighted in bold.

Customize the following parameters for your application:

• Device used for communication

The DCS6 module supports two instances of SPI namely DCS6_PARAMS_DEV_SPI0 and DCS6_PARAMS_DEV_SPI1, two instances of I2C namely DCS6_PARAMS_DEV_I2C0 and DCS6_PARAMS_DEV_I2C1 and 3 instances of UART namely DCS6_PARAMS_DEV_UART0, DCS6_PARAMS_DEV_UART1 and DCS6_PARAMS_DEV_UART2. Chose the appropriate device used for control communication in the custom hardware.

• dmax/DSP processing for serial link control commands

The DCS6 module supports serial link control command processing on both dMAX (DCS6_PARAMS_PSLC_ENA) and DSP(DCS6_PARAMS_PSLC_DIS).

• dmax/DSP processing for read alpha commands

The DCS6 module supports processing of type 2, type 3 and type 4 read alpha commands on both dMAX(DCS6_PARAMS_PR_ENA) and DSP(DCS6_PARAMS_PR_DIS). The dMAX processing provides faster response time than the DSP processing. But for enabling this it has to be ensured that status structure for all algorithms are placed in L2RAM.

Modify DCS6_PARAMS_DEV

Modify DCS6_PARAMS_DEV for including the device prameters for the device used.

const DCS6_Params_Dev DCS6_PARAMS_DEV={
   /* Select the appropriate device from the following choices:
          DCS6_PARAMS_DEV_SPI - Select SPI device
          DCS6_PARAMS_DEV_I2C - Select I2C device
          DCS6_PARAMS_DEV_UART - Select UART device */
//    (Uint32)&DCS6_PARAMS_DEV_SPI,
//    (Uint32)&DCS6_PARAMS_DEV_I2C,
   (Uint32)&DCS6_PARAMS_DEV_UART,
};

Modify DCS6_PARAMS_DEV_SPI

Modify DCS6_PARAMS_DEV_SPI for SPI device configuraton if SPI is used for communication.

The DCS6 module allows the system integrator to control the SPI device configuration through the following parameters:

typedef struct DCS6_Params_Dev_Spi{
   Uint32 size;    /* size of the structure */
   Uint8 clen;     /* character length */
   Uint8 np;       /* number of pins */
   Uint8 pol;      /* clock polarity */ 
   Uint8 pha;      /* clock phase */
   Uint8 enahiz;   /* SPIENA pin mode */
   Uint8 res[3];   /* reserved */
   Uint32 emask;   /* error mask */
}DCS6_Params_Dev_Spi;

Details on all the different parameters and supported options are available in DCS6 documentation. Customize the following parameters for your application:

• character length

The DCS6 module supports SPI character length of 8 bits (DCS6_PARAMS_DEV_SPI_CLEN_8) and 16 bits (DCS6_PARAMS_DEV_SPI_CLEN_16). Chose as appropriate to interface with different SPI master devices.

• number of pins

The DCS6 module supports SPI communication with pin combinations as described below:

• DCS6_PARAMS_DEV_SPI_NP_3 - SPI 3 pin mode using SPISIMO, SPISOMI and SPICLK pins
• DCS6_PARAMS_DEV_SPI_NP_4_SCS - SPI 4 pin mode using SPISIMO, SPISOMI, SPICLK and SPISCS pins
• DCS6_PARAMS_DEV_SPI_NP_4_ENA - SPI 4 pin mode using SPISIMO, SPISOMI, SPICLK and SPIENA pins
• DCS6_PARAMS_DEV_SPI_NP_5 - SPI 5 pin mode using SPISIMO, SPISOMI, SPICLK, SPISCS and SPIENA pins
• DCS6_PARAMS_DEV_SPI_NP_5_SRDY - SPI 5 pin mode using SPISIMO, SPISOMI, SPICLK, SPISCS and SPIENA pins with SPIENA pin configured in general purpose output mode and driven as per the receive buffer watermark parameters.

• Clock polarity

The DCS6 module supports SPI communication with SPICLK signal polarity settings as described below:

• DCS6_PARAMS_DEV_SPI_POL_LOW - SPICLK signal is low inactive
• DCS6_PARAMS_DEV_SPI_POL_HIGH - SPICLK signal is high inactive

• Clock Delay

The DCS6 module supports SPI communication with SPICLK signal delay settings as described below:

• DCS6_PARAMS_DEV_SPI_PHA_IN - SPICLK signal is not delayed with respect to the data stream. The first data bit is transmitted with the first clock edge and the first data bit is received with the second (inverse) clock edge.
• DCS6_PARAMS_DEV_SPI_PHA_OUT - SPICLK signal is delayed with respect to the data stream. The first data bit is transmitted before the first clock edge and the first data bit is received with the first clock edge.

• SPIENA signal mode jouer au poker

The DCS6 module supports SPI communication with SPIENA signal inactive state settings as described below.

• DCS6_PARAMS_DEV_SPI_ENAHIZ_DIS - SPIENA signal is pulled high when not active
• DCS6_PARAMS_DEV_SPI_ENAHIZ_ENA - SPIENA signal is in high-impedance when not active

• Error condition Mask

The DCS6 module detects and reports the following error conditions and different combinations of these error conditions for the SPI device.

• DCS6_PARAMS_DEV_SPI_EMASK_OVRN - SPI device receive data overrun error
• DCS6_PARAMS_DEV_SPI_EMASK_BITERR - SPI device bit mismatch error
• DCS6_PARAMS_DEV_SPI_EMASK_DLENERR - SPI device data length error

Modify DCS6_PARAMS_DEV_I2C

Modify DCS6_PARAMS_DEV_I2C for I2C device configuraton if I2C is used for communication.

The DCS6 module allows the system integrator to control the I2C device configuration through the following parameters:

typedef struct DCS6_Params_Dev_I2c{
   Uint32 size;    /* size of the structure */
   Uint32 icoar;   /* slave address */
   Uint32 icpsc;   /* prescale */
   Uint32 icclkl;  /* clock low */
   Uint32 icclkh;  /* clock high */
   Uint32 emask;   /* error mask */
}DCS6_Params_Dev_I2c;

The parameters specified here are applicable for all instances of the I2C device. For decription of all individual parameters; refer DCS6 documnentation.

Customize DCS6_PARAMS_DEV_I2C for the following parameters for your application:

• Own slave address

The DCS6 module uses this parameter to configure the I2C slave address in the ICOAR register. The master should use this address to communicate with the DCS6 module I2C slave device. The DCS6 module recommends the following slave addresses to avoid conflicts:

• DCS6_PARAMS_DEV_I2C0_OA - Slave address for I2C instance 0 (DCS6_PARAMS_DEV_I2C0)
• DCS6_PARAMS_DEV_I2C1_OA - Slave address for I2C instance 1 (DCS6_PARAMS_DEV_I2C1)

Modify DCS6_PARAMS_DEV_UART

Modify DCS6_PARAMS_DEV_UART for UART device configuraton if UART is used for communication.

The DCS6 module supports UART communication using 1 START bit, 8 DATA (ascii) bits, no PARITY bit and 1 STOP bit with software (Xon/Xoff) flow control. The DCS6 module uses the UART data pins (UART_TXD, UART_RXD) for communication. The UART_CTS and UART_RTS pins are not used for handshaking, instead the flow control is achieved by using special characters (Xon - 0x11 / Xoff - 0x13) on the data bus. The communication baud rate is configurable and can be set to the desired rate using the parameters described below.

The DCS6 module allows the system integrator to control the UART device configuration through the following parameters:

typedef struct DCS6_Params_Dev_Uart{
   Uint32 size;    /* size of the structure */
   Uint32 dll;     /* divisor lsb latch */
   Uint32 dlh;     /* divisor msb latch */
   Uint32 mdr;     /* mode definition */
   Uint32 fl;      /* fifo level */
   Uint16 xrxSize; /* ascii receive buffer size */
   Uint16 xtxSize; /* ascii transmit buffer size */
   Uint32 emask;   /* error mask */
}DCS6_Params_Dev_Uart;

The parameters specified here are applicable for all instances of the UART device. For description of all individual parameters refer DCS6 documentation.

Customize DCS6_PARAMS_DEV_UART for the following parameters for your application:

• divisor lsb latch value

The DCS6 module uses this value to configure the UART DLL register. The DCS6 module defines the following divisor values for the commonly used baud rates:

• DCS6_PARAMS_DEV_UART_DIV_16X_B2400 - 2400 baud rate with 16x oversampling
• DCS6_PARAMS_DEV_UART_DIV_16X_B4800 - 4800 baud rate with 16x oversampling
• DCS6_PARAMS_DEV_UART_DIV_16X_B9600 - 9600 baud rate with 16x oversampling
• DCS6_PARAMS_DEV_UART_DIV_16X_B19200 - 19200 baud rate with 16x oversampling
• DCS6_PARAMS_DEV_UART_DIV_16X_B38400 - 38400 baud rate with 16x oversampling
• DCS6_PARAMS_DEV_UART_DIV_16X_B57600 - 57600 baud rate with 16x oversampling
• DCS6_PARAMS_DEV_UART_DIV_16X_B115200 - 115200 baud rate with 16x oversampling
• DCS6_PARAMS_DEV_UART_DIV_13X_B2400 - 2400 baud rate with 13x oversampling
• DCS6_PARAMS_DEV_UART_DIV_13X_B4800 - 4800 baud rate with 13x oversampling
• DCS6_PARAMS_DEV_UART_DIV_13X_B9600 - 9600 baud rate with 13x oversampling
• DCS6_PARAMS_DEV_UART_DIV_13X_B19200 - 19200 baud rate with 13x oversampling
• DCS6_PARAMS_DEV_UART_DIV_13X_B38400 - 38400 baud rate with 13x oversampling
• DCS6_PARAMS_DEV_UART_DIV_13X_B57600 - 57600 baud rate with 13x oversampling
• DCS6_PARAMS_DEV_UART_DIV_13X_B115200 - 115200 baud rate with 13x oversampling

The above divisor values are computed using UART input clock of 150 MHz. If the UART input clock is configured differently or if the desired baud rate does not match any of the above then refer the UART User Guide for information on computing the divisor value.

• divisor msb latch value

The DCS6 module uses this value to configure the UART DLH register. Refer the description of dll parameter above for information on the commonly used baud rates and the corresponding divisor values.

• mode definition

The mode definition defines the UART oversampling mode and is used to configure the UART MDR register. The DCS6 modules supports the following mode definitions:

• DCS6_PARAMS_DEV_UART_MDR_OSMSEL_16X - 16x oversampling mode
• DCS6_PARAMS_DEV_UART_MDR_OSMSEL_13X - 13x oversampling mode

• fifo level

The DCS6 module supports the following UART fifo levels:

• DCS6_PARAMS_DEV_UART_FL_4 - 4 byte fifo
• DCS6_PARAMS_DEV_UART_FL_8 - 8 byte fifo
• DCS6_PARAMS_DEV_UART_FL_14 - 14 byte fifo

Customizing PA for SPI communication on DA8xx EVM

DCS6 module provides the ability to control the PA software running on DA8xx EVM with SPI, I2C and UART peripherals. The DCS6 SPI demonstration setup requires DA8xx EVM and DA7xx EVM controller card. The DA7xx EVM controller card need some updates for interfacing with the DA8xx device. Update the controller card as per the the XK-IP5 package available with SDK in {SDK_INSTALL_DIR}\tools\xk-ip5_[DATE].zip. Follow below steps for I2C communication for DA8xx EVM:

• Refer {SDK_INSTALL_DIR}\pa\doc\dcs6_hwsetup.html for hardware setup with DA8xx EVM and DA7xx controller card for SPI communication.
• Modify dcs6_params.c for SPI0 communication as described in above sections.
• Modify board_init.c to enable code to route SPI0 signals to the serial expansion connector as below(By default this routing is disabled):

   // Route the SPI0 signals to the serial expansion connector for
   // DCS6 SPI communication
   // i2c0 is used to configure the PCF8574APWRG4 on UI card which in turn controls the SPI_MODE signal.
   if(1){
       unsigned int * i2c0_ptr=(unsigned int *)0x01C22000u;
       i2c0_ptr[9]=0; 			// resetting peripheral by writing 0 to i2c mode reg.
       i2c0_ptr[12]=2;			// writing to i2c prescaler reg.
       i2c0_ptr[3]=6;			// writing to i2c clock low-time divider reg.
       i2c0_ptr[4]=6;			// writing to i2c clock high-time divider reg.
       i2c0_ptr[9]=0x00000020;		// enabling i2c peripheral by writing 1 to IRS bit of the mode reg. 
       i2c0_ptr[7]=0x3F;		// populating the slave address 0x3F to i2c slave address reg.
       i2c0_ptr[9]|=0x00000600;	// configured the i2c0 as master and transmitter by writing to i2c mode reg.
       i2c0_ptr[5]=1;			// writing 1 to i2c data count reg.
       while(i2c0_ptr[2]&0x00001000);	// polling i2c interrupt status register to see whether bus is busy.
       while(!(i2c0_ptr[2]&0x00000010)); // checking whether ICXRDY bit is set.
       i2c0_ptr[8]=0x7F;		// writing 0x7F to i2c data transmit reg.
       i2c0_ptr[9]|=0x00002800;	// configured to send START/STOP bit by writing to STT and STP bits of mode reg.
       while(i2c0_ptr[2]&0x00001000);	// polling i2c interrupt status reg to see if the bus is busy!
       while(i2c0_ptr[9]&0x00000400);	// checking whether transfer is completed. wait for MST bit to be 0 in mode reg.    
   }

Customizing PA for I2C communication on DA8xx EVM

DCS6 module provides the ability to control the PA software running on DA8xx EVM with SPI, I2C and UART peripherals. The DCS6 I2C demonstration setup requires DA8xx EVM and DA7xx EVM controller card. The DA7xx EVM controller card need some updates for interfacing with the DA8xx device. Update the controller card as per the the XK-IP5 package available with SDK in {SDK_INSTALL_DIR}\tools\xk-ip5_[DATE].zip. The steps below describes how to get I2C communication up on DA8xx EVM:

• Refer {SDK_INSTALL_DIR}\pa\doc\dcs6_hwsetup.html for hardware setup with DA8xx EVM and DA7xx controller card for I2C communication.
• Modify dcs6_params.c for I2C0 communication as described in above sections.
• Modify board_init.c to disable code to route SPI0 signals to the serial expansion connector as below(By default this routing is disabled):

   // Route the SPI0 signals to the serial expansion connector for
   // DCS6 SPI communication
   // i2c0 is used to configure the PCF8574APWRG4 on UI card which in turn controls the SPI_MODE signal.
   if(0) {
       unsigned int * i2c0_ptr=(unsigned int *)0x01C22000u;
       i2c0_ptr[9]=0; 			// resetting peripheral by writing 0 to i2c mode reg.
       i2c0_ptr[12]=2;			// writing to i2c prescaler reg.
       i2c0_ptr[3]=6;			// writing to i2c clock low-time divider reg.
       i2c0_ptr[4]=6;			// writing to i2c clock high-time divider reg.
       i2c0_ptr[9]=0x00000020;		// enabling i2c peripheral by writing 1 to IRS bit of the mode reg. 
       i2c0_ptr[7]=0x3F;		// populating the slave address 0x3F to i2c slave address reg.
       i2c0_ptr[9]|=0x00000600;	// configured the i2c0 as master and transmitter by writing to i2c mode reg.
       i2c0_ptr[5]=1;			// writing 1 to i2c data count reg.
       while(i2c0_ptr[2]&0x00001000);	// polling i2c interrupt status register to see whether bus is busy.
       while(!(i2c0_ptr[2]&0x00000010)); // checking whether ICXRDY bit is set.
       i2c0_ptr[8]=0x7F;		// writing 0x7F to i2c data transmit reg.
       i2c0_ptr[9]|=0x00002800;	// configured to send START/STOP bit by writing to STT and STP bits of mode reg.
       while(i2c0_ptr[2]&0x00001000);	// polling i2c interrupt status reg to see if the bus is busy!
       while(i2c0_ptr[9]&0x00000400);	// checking whether transfer is completed. wait for MST bit to be 0 in mode reg.    
   }

References

1. DCS6 Parameters, TI Performance Audio
2. dcs6_params.c, TI Performance Audio
3. dcs6_params.h, TI Performance Audio