DA8xx Audio I/O Customization

Introduction

This page talks Audio I/O customization with an example. Almost all cases, I/O customization is needed to port to the target H/W. In this section, customization of mult-channel analog I/O is described mainly. There is some comments about DIR/DIT, but you can use just copy of dap_e5.h and dap_e5.c. except for pin assigment.
Though this page assuming i14 case but less difference with y13 case.

• Topololgy: I
• Input:
  • DIR input (McASP0 AXR0[9] slave)
  • Analog 8ch input(McASP1 AXR1[0,1,2,10] slave)
• Output:
  • Analog 8ch output (McASP1 AXR1[8,7,6,5] master)
  • DIT 2ch output (McASP2 AXR2[0], master )
• 512fs
• DIR, ADC and DAC are controlled by uC (not DSP)
• format 16/24bit I2S (DIR)ls

Figure1: Example Audio Clocking and format

Procedure

For more information please check DA8xx Audio I/O Customization Software Structures

Step 1 : Edit T:\pa\cust\vender\c999\i14\cus\dap_cus.h

In this step, you should declare I/O setting object which will be used dap_cus.c and io.c

 struct DAP_E17_Rx_Params_
 {
   XDAS_UInt16 mode;
   XDAS_UInt8 unused[2];
 };
 
 typedef struct DAP_E17_Rx_Params
 {
   Int size;                           // Type-specific size
   struct DXX_Params_ sio;             // Common parameters
   struct DAP_Params_ dap;             // Device parameters
   struct DAP_E17_Rx_Params_ e17rx;    // Board Receive parameters
 } DAP_E17_Rx_Params;
 
 /* Edit or Add Rx parameters that you want to use */
 extern const DAP_E17_Rx_Params DAP_E17_RX_DIR;
 extern const DAP_E17_Rx_Params DAP_E17_RX_ADC_48000HZ_Custom;

 struct DAP_E17_Tx_Params_
 {
   XDAS_UInt8 divider;
   XDAS_UInt8 unused[3];
 };
 
 typedef struct DAP_E17_Tx_Params
 {
   Int size;                           // Type-specific size
   struct DXX_Params_ sio;             // Common parameters
   struct DAP_Params_ dap;             // Device parameters
   struct DAP_E17_Tx_Params_ e17tx;    // Board Transmit parameters
 } DAP_E17_Tx_Params;
 
 /* Edit or Add Tx parameters that you want to use */
 extern const DAP_E17_Rx_Params DAP_E17_TX_DAC_Custom;
 extern const DAP_E17_Tx_Params DAP_E17_TX_DIT;

Step 2 : Edit T:\pa\cust\vender\c999\i14\cus\dap_cus.c

• In this step, McASP register configuration is described. (a)Analog Rx/Tx of Left Justified, (b)Right Justified and (c)I2S RExample of Audio Data format for Serial Port. Parameters are for (c) but there is some comments to change (a) or (b)

ple of Audio Data format for Serial Port

 /* McASP Setting for ADC */
 static const MCASP_ConfigRcv rxConfigADCCustom =
 {
   MCASP_RMASK_OF(0xFFFFFFFF),            // Bit mask. In this case, not masked all bit
   MCASP_RFMT_RMK(                        
       MCASP_RFMT_RDATDLY_1BIT,           // 1 BIT delay is needed for (c) format, for (a) or (b)
                                          // MCASP_RFMT_RDATDLY_0BIT should be used
       MCASP_RFMT_RRVRS_MSBFIRST,         // MSB first for all example format
       MCASP_RFMT_RPAD_RPBIT,             // Pad extra bits with specified by RPBIT
       MCASP_RFMT_RPBIT_OF(0),            // Pad with bit 0 value
       MCASP_RFMT_RSSZ_32BITS,            // Slot size is 32bit
       MCASP_RFMT_RBUSEL_DAT,             // Use DMA port
       MCASP_RFMT_RROT_NONE),             // No right rotation for (c) and (a),
                                          // (b) needs MCASP_RFMT_RROT_OF(24) in case of 24bit
   MCASP_AFSRCTL_RMK(                     
       MCASP_AFSRCTL_RMOD_OF(2),          // 2 slot TDM Mode for stereo input
       MCASP_AFSRCTL_FRWID_WORD,          // Frame sync width is single word
       MCASP_AFSRCTL_FSRM_EXTERNAL,       // External LRCK
                                          // If DSP is "master", you shouls use MCASP_AFSRCTL_FSRM_INTERNAL
       MCASP_AFSRCTL_FSRP_ACTIVELOW),     // Falling edge on Rx frame sync is the beginning of a frame for (c),
                                          // MCASP_AFSRCTL_FSRP_ACTIVEHIGH is used for (a) and (b)
   MCASP_ACLKRCTL_RMK(                    
       MCASP_ACLKRCTL_CLKRP_RISING,       // Receiver samples data on the rising edge of the bit clock
       MCASP_ACLKRCTL_CLKRM_EXTERNAL,     // External BCLK
                                          // If DSP is "master", you shouls use MCASP_ACLKRCTL_CLKRM_INTERNAL 
       MCASP_ACLKRCTL_CLKRDIV_DEFAULT),   // Divide by 1 (= not divide).
                                          // If DSP is "master", you many need to divide 
   MCASP_AHCLKRCTL_RMK(                   
       MCASP_AHCLKRCTL_HCLKRM_EXTERNAL,   // External High rate clock.
                                          // This is set but actually isn't used in case of DSP slave.                                     // If DSP is master and use external clock as reference
                                          // the same setting can be used.
       MCASP_AHCLKRCTL_HCLKRP_RISING,     // AHCLKR is not inverted before programmable bit clock divider
       MCASP_AHCLKRCTL_HCLKRDIV_DEFAULT), // Divide by 1 (= not divide)
   MCASP_RTDM_OF(3),                      // RTDM slot 0 and slot 1 is active
   MCASP_RINTCTL_DEFAULT,                 // All disabled at default
   MCASP_RCLKCHK_DEFAULT                  // All 0 at default
 };

 /* McASP Setting for DAC */
 static const MCASP_ConfigXmt txConfigDACCustom =
 {
   MCASP_XMASK_OF(0x00FFFFFF),            // Bit mask. In this case, only 24bits are valid
   MCASP_XFMT_RMK(                        
       MCASP_XFMT_XDATDLY_1BIT,           // 1 BIT delay is needed for (c) format, for (a) or (b)
                                          // MCASP_XFMT_XDATDLY_0BIT should be used
       MCASP_XFMT_XRVRS_MSBFIRST,         // MSB first for all example format
       MCASP_XFMT_XPAD_ZERO,              // Pad extra bits with 0
       MCASP_XFMT_XPBIT_DEFAULT,          // Pad with bit 0 value
       MCASP_XFMT_XSSZ_32BITS,            // Slot size is 32bit
       MCASP_XFMT_XBUSEL_DAT,             // Use DMA port
       MCASP_XFMT_XROT_24BITS),           // 24bit right rotation for (c) and (a),
                                          // (b) needs MCASP_XFMT_XROT_NONE in case of 24bit
   MCASP_AFSXCTL_RMK(                     
       MCASP_AFSXCTL_XMOD_OF(2),          // 2 slot TDM (I2S) Mode
       MCASP_AFSXCTL_FXWID_WORD,          // Frame sync width is single word
       MCASP_AFSXCTL_FSXM_INTERNAL,       // Internal LRCK. If DSP is "slave" you can use
                                          // MCASP_AFSXCTL_FSXM_EXTERNAL
       MCASP_AFSXCTL_FSXP_ACTIVELOW),     // Falling edge on Tx frame sync is the beginning of a frame for (c)
                                          // MCASP_AFSXCTL_FSXP_ACTIVEHIGH is used for (a) and (b)
   MCASP_ACLKXCTL_RMK(                    
       MCASP_ACLKXCTL_CLKXP_FALLING,      // Transmit samples data on the falling edge of the bit clock
       MCASP_ACLKXCTL_ASYNC_ASYNC,        // Asynchronous separate clock and frame sync used by Tx and Rx
       MCASP_ACLKXCTL_CLKXM_INTERNAL,     // Internal BCLK
                                          // If DSP is "slave", you shouls use MCASP_ACLKXCTL_CLKXM_EXTERNAL
       MCASP_ACLKXCTL_CLKXDIV_DEFAULT),   // Divide by 1 (= not divide). This bit is set at CUS_dapControl()
   MCASP_AHCLKXCTL_RMK(                   
       MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,   // External High rate clock as a reference clock.
                                          // MCASP_AHCLKXCTL_HCLKXM_INTERNAL can be used if
                                          // you use DSP master clock as audio reference clock
                                          // but Rx should also use DSP master clock in this case.
       MCASP_AHCLKXCTL_HCLKXP_FALLING,    // AHCLKR is inverted before programmable bit clock divider
       MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),   // Divide by 1 (= not divide)
   MCASP_XTDM_OF(3),                      // XTDM slot 0 and slot 1 is active
   MCASP_XINTCTL_DEFAULT,                 // All disabled at default
   MCASP_XCLKCHK_DEFAULT                  // All 0 at default
 };

• Here is the definition of parameter that is declared in dap_cus.h. These are I/O configuration parameters

 /* DAP Input Parameter Definitions */
 const DAP_E17_Rx_Params DAP_E17_RX_ADC_48000HZ_Custom =
 {
   sizeof (DAP_E17_Rx_Params),      // size
   "DAP",                           // name
   MCASP_DEV1,                      // moduleNum --> mcasp #
   (Void *)&rxConfigADCCustom,      // pConfig
   -1,                              // wordSize (unused)
   -1,                              // precision (unused)
   E17_dapControl,                  // control
   0xA0000407,                      // pinMask (ACLKR1, AFSR1, AXR[10], AXR[2], AXR[1], AXR[0])
   0,                               // mode (unused)
   0,0                              // unused[2]
 };

 /* DAP Output Parameter Definitions */
 const DAP_E17_Tx_Params DAP_E17_TX_DAC_Custom =
 {
   sizeof (DAP_E17_Tx_Params),   // size
   "DAP",                        // name
   MCASP_DEV1,                   // moduleNum --> mcasp #
   (Void *)&txConfigDACCustom,   // pConfig
   3,                            // wordSize (in bytes)
   24,                           // precision (in bits)
   E17_dapControl,               // control
   0x1C0001e0,                   // pinMask (ACLKX1, AHCLKX1, AFSX1, AXR1[8], AXR1[7], AXR[6], AXR[5])
   8,                            // divider: to make 64fs from 512fs
   0,0,0                         // unused[3]
 };

• CUS_dapControl function is declared here.

 /* Define custom dapControl function */
 XDAS_Int32 CUS_dapControl (DEV_Handle device, const PAF_SIO_Params *pParams, XDAS_Int32 code, XDAS_Int32 arg);

• Here is definition of CUS_dapControl. This function mainly do as belows
  • Set default input status
  • Set output divider value

 /* This function is called by the peripheral driver (DAP) in response to various SIO_ctrl() calls made by the framework.*/
 
 XDAS_Int32 CUS_dapControl (DEV_Handle device, const PAF_SIO_Params * pParams, XDAS_Int32 code, XDAS_Int32 arg)
 {
   const DAP_CUS_Rx_Params *pDapCusRxParams = (const DAP_CUS_Rx_Params *) pParams;
   const DAP_CUS_Tx_Params *pDapCusTxParams = (const DAP_CUS_Tx_Params *) pParams;
   volatile Uint32 *mcasp = mcaspAddr[pParams->sio.moduleNum];
   float ratex;
   XDAS_Int32 divider;
   float clkDiv;
   
   switch (code)
   {
     // This case provides a regular entry point for managing the specifiec input device. Nominally, this is used to provide lock and sample rate
     // status to the framework.
     
     case PAF_SIO_CONTROL_GET_INPUT_STATUS:
       if (device->mode != DEV_INPUT)
         return SYS_EINVAL;
         
       if (pDapCusRxParams == NULL || pDapCusRxParams->size != sizeof (DAP_CUS_Rx_Params))
         return (SYS_EBADIO);
       
       {
         PAF_SIO_InputStatus *pOut = (Void *) arg;
         
         pOut->lock = 1;
         pOut->nonaudio = PAF_IEC_AUDIOMODE_UNKNOWN;
         pOut->emphasis = PAF_IEC_PREEMPHASIS_UNKNOWN;
         pOut->sampleRateMeasured = PAF_SAMPLERATE_48000HZ;
         pOut->sampleRateData = PAF_SAMPLERATE_48000HZ;
       }
       break;
       
     // This case provides a regular entry point for managing the specified
     // output device. Nominally this is used to change the output clock dividers
     // in the case of double rate output (e.g. DTS 96/24).
       
     case PAF_SIO_CONTROL_SET_RATEX:
       
       // Support only output rate control, for now
       if (device->mode != DEV_OUTPUT)
         return (SYS_EINVAL);
          
       ratex = *((float *) arg);
        
       // Force ratex to an integral value to allow 44.1 & 48 kHz interplay.
       // Does not allow 32 & 48 kHz or 32 & 44.1 kHz interplay.
       if (ratex < .354)
          ratex = 0.25;
       else if (ratex < .707)
          ratex = 0.50;
       else if (ratex < 1.414)
          ratex = 1.00;
       else if (ratex < 2.828)
          ratex = 2.00;
       else
          ratex = 4.00;
        
       clkDiv = pDapCusTxParams->tx.divider * 1.0f;
        
       divider = clkDiv / ratex;
        
       // DIT requires 2x clock
       if ((mcasp[_MCASP_AFSXCTL_OFFSET] & _MCASP_AFSXCTL_XMOD_MASK) == (MCASP_AFSXCTL_XMOD_OF (0x180) << _MCASP_AFSXCTL_XMOD_SHIFT))
       {
         if (divider < 2)
           return (SYS_EINVAL);
         divider >>= 1;
       }
        
       // Configure
       mcasp[_MCASP_ACLKXCTL_OFFSET] =
           (mcasp[_MCASP_ACLKXCTL_OFFSET] & ~_MCASP_ACLKXCTL_CLKXDIV_MASK)
              | (MCASP_ACLKXCTL_CLKXDIV_OF (divider - 1) << _MCASP_ACLKXCTL_CLKXDIV_SHIFT);
         
         break;
         
     // Basically, following case is not needed to care. Just keep empty cases
     case PAF_SIO_CONTROL_OPEN:
       break;
       
     case PAF_SIO_CONTROL_CLOSE:
       break;
       
     case PAF_SIO_CONTROL_MUTE:
       break;
       
     case PAF_SIO_CONTROL_UNMUTE:
       break;
       
     case PAF_SIO_CONTROL_IDLE:
       break;
       
     case PAF_SIO_CONTROL_WATCHDOG:
       break;
       
     case PAF_SIO_CONTROL_SET_DITSTATUS:
       // No action necessary.
       break;
       
     // Any other cases are not handled and return an error.
         
     default:
       return SYS_EINVAL;
   }
   
   return (SYS_OK);
 } // CUS_dapControl

Step 3. Editing T:\pa\cust\vender\c999\i14\cus\io.c

• This file is specified I/O shortcut. To change I/O setting, you should send some command. To simplify the sequence, shortcut is created and you can send just one command for I/O setting

 /* Input device configurations & shortcut definitions */
 // .............................................................................
 // Note that CUS_SIGMAXX means last two digit of 0xf1XX.
 // ex. CUS_SIGMA32_S is for 0x20 of 0xf120
 // 32 = 0x20 of 0xf120
 // 33 = 0x21 of 0xf121
 // ....
 // .............................................................................  
 const struct
 {
   Int n;
   const PAF_SIO_Params *x[DEVIN_N];
 } patchs_devin[1] =
 {
   DEVIN_N,
       // These values reflect the definitions DEVIN_* in pa*io_a.h:        NULL,                                               // InNone
       (const PAF_SIO_Params *) &DAP_E17_RX_DIR,           // InDigital
       (const PAF_SIO_Params *) &DAP_E17_RX_ADC_48000HZ_Custom,   // InAnalog
 };
 
 // execPAIInAnalogCustom
 #define CUS_SIGMA34_S \
   writeDECSourceSelectNone, \
   writePA3Await(rb32DECSourceDecode,ob32DECSourceDecodeNone), \
   writePCMChannelConfigurationProgramSurround4_1, \  <- Set input channel configuration
   writePCMScaleVolumeN(0), \                       
   writeDECChannelMapFrom16(0,4,1,5,2,6,3,7,-3,-3,-3,-3,-3,-3,-3,-3), \ <- Please refer Channel Map
   writeIBEmphasisOverrideNo, \
   writeIBPrecisionOverride24, \
   writeIBSampleRateOverride48000Hz, \
   writeIBSioSelectN(DEVINP_ADC1), \ <- Defined in pa_i14_cXX_io_a.h
   writeDECSourceSelectPCM,        \ <- Only PCM input is expceted
   0xcdf0,execPAIInAnalog
 
 #pragma DATA_SECTION(cus_sigma34_s0, ".none")
 const ACP_Unit cus_sigma34_s0[] = {
   0xc900 + 0 - 1,
   CUS_SIGMA34_S,
 };
 
 const ACP_Unit cus_sigma34_s[] = {
   0xc900 + sizeof (cus_sigma34_s0) / 2 - 1,
   CUS_SIGMA34_S,
 };

 /* Output device configurations & shortcut definitions */
 const struct
 {
   Int n;
   const PAF_SIO_Params *x[DEVOUT_N];
 } patchs_devout[1] =
 {
   DEVOUT_N,
       // These values reflect the definitions DEVOUT_* in pa*io_a.h:
       NULL,                                               // OutNone
       (const PAF_SIO_Params *) &DAP_E17_TX_DAC_Custom,    // OutAnalog
       (const PAF_SIO_Params *) &DAP_E17_TX_DIT,           // OutDigital
 };
 
 // .............................................................................
 // execPAIOutAnalogCustom
 #define CUS_SIGMA49_S \
   rb32DECSourceSelect_3, \
   writeDECSourceSelectNone, \
   writePA3Await(rb32DECSourceDecode,ob32DECSourceDecodeNone), \
   writeOBSioSelectN(DEVOUT_DAC), \ <- Defined in pa_i14_cXX_io_a.h
   writeENCChannelMapTo16(3,7,2,6,1,5,0,4,-3,-3,-3,-3,-3,-3,-3,-3), \ See Channel Map
   wb32DECSourceSelect_3, \
   0xcdf0,execPAIOutAnalogCustom
 
 #pragma DATA_SECTION(cus_sigma49_s0, ".none")
 const ACP_Unit cus_sigma49_s0[] = {
   0xc900 + 0 - 1,
   CUS_SIGMA49_S,
 };
 
 const ACP_Unit cus_sigma49_s[] = {
   0xc900 + sizeof (cus_sigma49_s0) / 2 - 1,
   CUS_SIGMA49_S,
 };

• Here is Y topology output example. Input is almost same as I topology, Just change 'I' to 'Y'.

 /* Output device configurations & shortcut definitions */
 const struct
 {
   Int n;
   const PAF_SIO_Params *x[DEVOUT_N];
 } patchs_devout[1] =
 {
   DEVOUT_N,
       // These values reflect the definitions DEVOUT_* in pa*io_a.h:
       NULL,                                               // OutNone
       (const PAF_SIO_Params *) &DAP_E17_TX_DAC_Custom,    // OutAnalog
       (const PAF_SIO_Params *) &DAP_E17_TX_DIT,           // OutDigital
 };
 
 // .............................................................................
 // execPAYOutPrimaryAnalogCustom
 #define CUS_SIGMA49_S \
   rb32DECSourceSelect_3, \
   writeDECSourceSelectNone, \
   writePA3Await(rb32DECSourceDecode,ob32DECSourceDecodeNone), \
   writeOBSioSelectN(DEVOUT_DAC), \ <- Defined in pa_i14_cXX_io_a.h
   writeENCChannelMapTo16(3,7,2,6,1,5,0,4,-3,-3,-3,-3,-3,-3,-3,-3), \ See Channel Map
   wb32DECSourceSelect_3, \
   0xcdf0,execPAYOutPrimaryAnalogCustom
 
 #pragma DATA_SECTION(cus_sigma49_s0, ".none")
 const ACP_Unit cus_sigma49_s0[] = {
   0xc900 + 0 - 1,
   CUS_SIGMA49_S,
 };
 
 const ACP_Unit cus_sigma49_s[] = {
   0xc900 + sizeof (cus_sigma49_s0) / 2 - 1,
   CUS_SIGMA49_S,
 };

Step 4. Editing T:\pa\cust\vender\c999\i14\cus\alpha\pa_i14_cXX_io_a.h

• Here is the definition of I/O shortcut number which is referred in io.c

 // -----------------------------------------------------------------------------
 // IB SIO Select Register is set by the execPAIIn* shortcuts
 
 #define  execPAIInNone          0xf120
 #define  execPAIInDigital       0xf121 // DIR input
 #define  execPAIInAnalogCustom  0xf122 // 8ch analog input
 #define  execPAYInSing          0xf126 // Noise generation
 
 
 // These values reflect the definition of devinp[]
 #define DEVINP_NULL             0
 #define DEVINP_DIR              1
 #define DEVINP_ADC1             2
 #define DEVINP_N                3
 
 #define wroteIBSioCommandNone           0xca00+STD_BETA_IB,0x0500+DEVINP_NULL
 #define wroteIBSioCommandDigital        0xca00+STD_BETA_IB,0x0500+DEVINP_DIR
 #define wroteIBSioCommandAnalogCustom   0xca00+STD_BETA_IB,0x0500+DEVINP_ADC1
 
 
 #define wroteIBSioSelectNone            0xca00+STD_BETA_IB,0x0580+DEVINP_NULL
 #define wroteIBSioSelectDigital         0xca00+STD_BETA_IB,0x0580+DEVINP_DIR
 #define wroteIBSioSelectAnalogCustom    0xca00+STD_BETA_IB,0x0580+DEVINP_ADC1
 
 
 
 // -----------------------------------------------------------------------------
 // OB SIO Select Register is set by the execPA17IOut* shortcuts
 
 #define  execPAIOutNone                 0xf130
 #define  execPAIOutAnalogCustom         0xf131 //8 channel output analog (24bit)
 #define  execPAIOutDigital            0xf133 //2 channel output DIT    (24bit)
 
 
 // These values reflect the definition of devout[]
 #define DEVOUT_NULL             0
 #define DEVOUT_DAC              1
 #define DEVOUT_DIT              2
 #define DEVOUT_N                3

• Here is the example of Y topology ouput. Input is almost same as I topology. Just change 'I' to 'Y'

 // -----------------------------------------------------------------------------
 // OB SIO Select Register is set by the execPA17YOut* shortcuts
 
 #define  execPAYOutPrimaryNone                 0xf130
 #define  execPAYOutPrimaryAnalogCustom         0xf131 //8 channel output analog (24bit)
 #define  execPAYOutSecondaryNone               0xf132
 #define  execPAYOutSecondaryDigital            0xf133 //2 channel output DIT    (24bit)
 
 
 // These values reflect the definition of devout[]
 #define DEVOUT_NULL             0
 #define DEVOUT_DAC              1
 #define DEVOUT_DIT              2
 #define DEVOUT_N                3
 
 
 #define wroteOBSioCommandNone                0xca00+STD_BETA_OB,0x0500+DEVOUT_NULL
 #define wroteOBSioCommandAnalogCustom        0xca00+STD_BETA_OB,0x0500+DEVOUT_DAC
 #define wroteOBSioCommandDigital             0xca00+STD_BETA_OB,0x0500+DEVOUT_DIT
 
 #define wroteOBSioSelectNone                 0xca00+STD_BETA_OB,0x0580+DEVOUT_NULL
 #define wroteOBSioSelectAnalogCustom         0xca00+STD_BETA_OB,0x0580+DEVOUT_DAC
 #define wroteOBSioSelectDigital              0xca00+STD_BETA_OB,0x0580+DEVOUT_DIT
 
   
 #define wroteOBSioCommandNone                0xca00+STD_BETA_OB,0x0500+DEVOUT_NULL
 #define wroteOBSioCommandAnalogCustom        0xca00+STD_BETA_OB,0x0500+DEVOUT_DAC
 #define wroteOBSioCommandDigital             0xca00+STD_BETA_OB,0x0500+DEVOUT_DIT
 
 #define wroteOBSioSelectNone                 0xca00+STD_BETA_OB,0x0580+DEVOUT_NULL
 #define wroteOBSioSelectAnalogCustom         0xca00+STD_BETA_OB,0x0580+DEVOUT_DAC
 #define wroteOBSioSelectDigital              0xca00+STD_BETA_OB,0x0580+DEVOUT_DIT

Channel Map

• Channel Map gives you a flexible mapping ability of input/output pin , in/out buffer and channel buffer. Here is the example of setting

writeDECChannelMapFrom16(FL, FR, SL, SR, C, SUBW, BL, BR, HL, HR, Rsv, Rsv, Rsv, Rsv, Rsv, Rsv)

• • This function can map each input pin and input buffer.
  • The relation between McASP pins and index is as follows. 0, ..., 7 is index of input buffer. Audio sample is read the order of index. (0->1->2->...->7)

• Example 1. Use writeDECChannelMapFrom16(0,4,1,5,2,6,3,7,-3,-3,-3,-3,-3,-3,-3,-3) to configure input pins as follows

 AXR1[0]  = FL/FR 
 AXR1[1]  = SL/SR
 AXR1[2]  = C/SUB
 AXR1[10] = BL/BR

• Example 2. Use writeDECChannelMapFrom16(0,4,2,6,1,5,3,7,-3,-3,-3,-3,-3,-3,-3,-3) to configure input pins as follows

to configure input pins as follows
 AXR1[0]  = FL/FR 
 AXR1[1]  = C/SUB
 AXR1[2]  = SL/SR
 AXR1[10] = BL/BR

writeENCChannelMapTo16(FL, FR, SL, SR, C, SUBW, BL, BR, HL, HR, Rsv, Rsv, Rsv, Rsv, Rsv, Rsv)

• • This function can map each output pin and output buffer.
  • The relation between McASP pins and index is as follows. 0, ..., 7 is index of output buffer. Audio sample is write the order of index. (0->1->2->...->7)

• Example 1. Use writeENCChannelMapTo16(0,4,1,5,2,6,3,7,-3,-3,-3,-3,-3,-3,-3,-3) to configure output pins as follows

 AXR1[0]  = FL/FR 
 AXR1[1]  = SL/SR
 AXR1[2]  = C/SUB
 AXR1[10] = BL/BR

• Example 2. Use writeENCChannelMapTo16(3,7,2,6,1,5,0,4,-3,-3,-3,-3,-3,-3,-3,-3) to configure output pins as follows

to configure input pins as follows
 AXR1[0]  = BL/BR 
 AXR1[1]  = SL/SR
 AXR1[2]  = C/SUB
 AXR1[10] = FL/FR

Others

• writeDECChannelMapTo16(0,1,8,9,2,12,10,11,4,5,14,15,-3,-3,-3,-3) and

writeENCChannelMapFrom16(0,1,8,9,2,12,10,11,4,5,14,15,-3,-3,-3,-3) are set at atboot.c

• writeDECChannelMapTo16 can map input buffer and channel buffer
• writeENCChannelMapFrom16 can map output buffer and channel buffer
  • You can change it but TI recommend not to change the relation to avoid confusion if you don't have specific reason. Most cases, writeDECChannelMapFrom16 and writeENCChannelMapTo16 is enough.

 left = 0, rght = 1, cntr = 2,  subw = 12
 lsur = 8, rsur = 9, lbak = 10, rbak = 11
 lwid = 4, rwid = 5, lhed = 14, rhed = 15