Changing DSPLink Memory Map

END OF LIFE

DSP Link is still available for download, but no further releases or updates are planned. Please see IPC Software Options for details and alternatives.

Introduction

DSPLink can be used by itself, or as part of Codec Engine (CE). This page gives details of changing the DSPLink memory map when used 'raw'. The instructions are applicable when using DSPLink version 1.4x onwards, where the dynamic configuration feature was added.

IMPORTANT: The details of changing DSPLink memory map when used within Codec Engine are available at this article.

Overview

The default DSPLink memory map for any platform usually assumes the following:

• 1 MB shared memory between ARM & DSP
• 1 MB DSP memory for DSP code and data

If the system integrator wishes to change the memory map, the following steps need to be taken:

• Update $(DSPLINK)/config/all/CFG_[PLATFORM].c to modify the memory map as per the ARM-DSP split requirements.
• Ensure that RESETVECTOR field in DSP config object is correctly modified.
• Modify $(DSPLINK)/dsp/inc/DspBios/$(DSPOSVERSION)/$(PLATFORM)/dsplink-[PLATFORM]-base.tci file to modify the memory map as per the configuration update.
• Ensure that the MAR configuration in the TCF file for cache matches the new memory map.
• On Linux, ensure that the mem=254M value passed to bootargs is updated to reserve the new amount of memory from Linux kernel for shared memory + DSP memory.

Example

Assume that you have 256 MB on your board. You want to split this as:

ARM: 64MB (0x4000000)
DSP: 192MB (0xC000000)

For this memory map, perform the following steps to modify default DSPLink configuration:

• Specify mem=64M on your Linux bootargs. This means you are saying that Linux (ARM) will use only the first 64MB. The last 196MB will be used by DSP & shared memory.

• The last address is 0x8FFFFFFF. So if the last 192MB is for DSP, you need to start DSP & shared memory space at:

84000000 = 0x90000000 - C000000

So your configuration will be: <syntaxhighlight lang = c>

   {
       0,                     /* ENTRY          : Entry number */
       "DSPLINKMEM",          /* NAME           : Name of the memory region */
       0x84000000,            /* ADDRPHYS       : Physical address */
       0x84000000,            /* ADDRDSPVIRT    : DSP virtual address */
       (Uint32) -1,           /* ADDRGPPVIRT    : GPP virtual address (if known) */
       0x5000,                /* SIZE           : Size of the memory region */
       TRUE                   /* SHARED         : Shared access memory? */
   },
   {
       1,                     /* ENTRY          : Entry number */
       "DSPLINKMEM1",         /* NAME           : Name of the memory region */
       0x84005000,            /* ADDRPHYS       : Physical address */
       0x84005000,            /* ADDRDSPVIRT    : DSP virtual address */
       (Uint32) -1,           /* ADDRGPPVIRT    : GPP virtual address (if known) */
       0xFB000,               /* SIZE           : Size of the memory region */
       TRUE                   /* SHARED         : Shared access memory? */
   },
   {
       2,                     /* ENTRY          : Entry number */
       "RESETCTRL",           /* NAME           : Name of the memory region */
       0x84100000,            /* ADDRPHYS       : Physical address */
       0x84100000,            /* ADDRDSPVIRT    : DSP virtual address */
       (Uint32) -1,           /* ADDRGPPVIRT    : GPP virtual address (if known) */
       0x00000080,            /* SIZE           : Size of the memory region */
       FALSE                  /* SHARED         : Shared access memory? */
   },
   {
       3,                     /* ENTRY          : Entry number */
       "DDR",                 /* NAME           : Name of the memory region */
       0x84100080,            /* ADDRPHYS       : Physical address */
       0x84100080,            /* ADDRDSPVIRT    : DSP virtual address */
       (Uint32) -1,           /* ADDRGPPVIRT    : GPP virtual address (if known) */
       0xBEFFF80,             /* SIZE           : Size of the memory region */
       FALSE                  /* SHARED         : Shared access memory? */
   },

</syntaxhighlight>

By doing this, you have reserved almost 191MB for DSP-side and 1MB for (DSPLINKMEM & DSPLINKMEM1) shared memory.

• Ensure that the RESETVECTOR field in LINKCFG_dspObjects structure is also changed to point to the right place.

<syntaxhighlight lang = c> STATIC CONST LINKCFG_Dsp LINKCFG_dspObjects [] = {

   {
       ...
       0x84100000,            /* RESETVECTOR    : Reset Vector for the DSP */
       ...
   }

} </syntaxhighlight>

• Correspondingly, DSP-side TCF file would have:

<syntaxhighlight lang='javascript'> /* ============================================================================

*  MEM : DSPLINKMEM
*  ============================================================================
*/

var DSPLINKMEM = prog.module("MEM").create("DSPLINKMEM"); DSPLINKMEM.base = 0x84000000; DSPLINKMEM.len = 0x100000; DSPLINKMEM.createHeap = false; DSPLINKMEM.comment = "DSPLINKMEM";

/* ============================================================================

*  MEM : RESET_VECTOR
*  ============================================================================
*/

var RESET_VECTOR = prog.module("MEM").create("RESET_VECTOR"); RESET_VECTOR.base = 0x84100000; RESET_VECTOR.len = 0x00000080; RESET_VECTOR.space = "code/data"; RESET_VECTOR.createHeap = false; RESET_VECTOR.comment = "RESET_VECTOR";

/* ============================================================================

*  MEM : DDR
*  ============================================================================
*/

var DDR = prog.module("MEM").create("DDR"); DDR.base = 0x84100080; DDR.len = 0x0BEFFF80; DDR.space = "code/data"; DDR.createHeap = true; DDR.heapSize = 0x10000; DDR.comment = "DDR"; </syntaxhighlight>

• You can even split up DDR into two or more memory segments on DSP-side if it makes more sense.

• You can now increase your heap size to whatever you need (keep in mind DSP/BIOS restrictions on heap size, if any).

• Ensure that you also change the MAR settings for DSP cache to match the new DSP memory map.

For default memory map of 0x8FE00000 to 0x8FFFFFFF, MAR 143 needs to be enabled: <syntaxhighlight lang='javascript'> prog.module("GBL").C64PLUSMAR128to159 = 0x00008000; </syntaxhighlight>

For the new memory map of 0x84000000 to 0x8FFFFFFF, MAR 132 to MAR 143 need to be enabled: <syntaxhighlight lang='javascript'> prog.module("GBL").C64PLUSMAR128to159 = 0x0000FFF0; </syntaxhighlight>

For this, refer to SPRU871 for MAR address ranges and DSP/BIOS documentation for syntax for the settings.