CC256x Schematic and Layout Checklist

Return to CC256x Main Wiki

Objective

This document will serve as a guideline in designing with TI's CC256x QFN family of devices. Making sure that each item in this checklist is met will ensure a more robust and successful design. This comprehensive checklist should be sufficient for streamlining the production process from schematic design to PCB layout.

*NEW* You can now check your design with the CC256x Checklist. The checklist enables you to verify your design in a series of easy-to-follow steps. The link to the checklist is below

Download - CC256x Checklist.zip

CC256x Schematic Checklist

This is a schematic checklist for TI's CC256x QFN Bluetooth family of devices. After completing the schematic design, this checklist can be used to quickly verify compliance with TI's reference design. This is based on the CC256x QFN EM Reference Design v1.2.

Nomenclature

Abbrev.	Meaning
IO, I/O	Input/Output
LDO	Low Drop Out
NC	Not Connected
device	CC256x QFN
de-cap	Decoupling Capacitor
DS	Datasheet

Power Supply

• VIO

1. Is VDD_IO connected to 1.8V power source?
2. Is there a 0.1uF decoupling cap for VDD_IO?
3. Check for max (1.92V), min (1.62V) values for VDD_IO? (See Sect. 4.1.2 in DS)

• VBAT

1. Are CL1.5_LDO_IN and MLDO_IN shorted together?
2. Is there a 1uF de-cap for VBAT?
3. Check for max (4.8V), min (2.2V), voltage dip values (400mV) for VBAT? (See Sect. 4.1.2 in DS)

• GND

1. Is the thermal pad EPAD (VSS_3) grounded?
2. Are VSS_FREF (B3), VSS_DCO (B11), VSS_1 (A24), VSS_2 (A28) grounded?

• LDO

1. Are the 4 MLDO_OUT_x pins shorted together?
2. Are the 4 MLDO_OUT_x pins connected to one 1uF de-cap?
3. Are the 7 DIG_LDO_OUT_x shorted together?
4. Are the 7 DIG_LDO_OUT_x connected to two 0.47uF and one 0.1uF de-cap?
5. Does each x_LDO_OUT(SRAM_LDO_OUT, ADCPPA_LDO_OUT, CL1.5_LDO_OUT, DCO_LDO_OUT) have a 0.1uF de-cap?

User Interfaces

• UART

1. Are the 4 HCI_x_1V8 pins interfaced as 1.8V I/O (otherwise include level shifters)?
2. Are the 4 HCI pins properly interfaced (HCI_RX connected to Host_TX, see above diagram)?
3. Is hardware flow control supported?
4. Is default UART baud rate (115.2Kbps) supported by host?
5. Verify UART IO states do not conflict when it is pulled up(PU) in shutdown mode in the CC256x(See Section 4.3.4 I/O States In Various Power Modes in DS)

I/O States In Some Power Modes

I/O Name	Shut Down	Deep Sleep	Active
HCI_RX	PU	PU	PU
HCI_TX	PU	-	-
HCI_RTS	PU	-	-
HCI_CTS	PU	PU	PU

• AUDIO

1. Are the 4 AUD_x_1V8 pins left floating (NC) if not using Hands Free Profile(HFP) or Assisted A2DP(A3DP)?
2. Are the 4 AUD_x_1V8 pins interfaced as 1.8V I/O (otherwise include level shifters)?
3. Verify Audio IO states do not conflict (See Section 4.3.4 I/O States In Various Power Modes in DS)

• DEBUG

1. Is the TX_DBG pin routed to an accessible test point for possible debugging?

• SHUTDOWN

1. Is the nSHUTDOWN pin controlled by 1.8V GPIO to control device reset?

Clock Interfaces

• Slow Clock

1. Is the SLOW_CLK_IN pin connected directly to a 32.768KHz external oscillator source?
2. Does the slow clock meet 250ppm?
3. Does the slow clock output correct voltage levels(1.8V) and waveform(square) as specifed in DS?

• Fast Clock

1. Is FREFP and FREFM connected directly to 26MHz crystal?
2. Does the fast clock meet 20ppm?
3. Are tuning caps properly placed (values determined by trace cap, crystal load cap, and input cap of pins)?

RF Output

• BT_RF

1. Are these NC pins grounded for better isolation of the RF trace: NC_2 (A10), NC_3 (A11),NC_14 (B9), NC_15 (B10)?
2. Is there a DC blocking cap(22pF) between BT_RF pin and BPF?
3. Does the BPF match Min Atten. Values as shown below? (See Section 4.1.2 in PCB Guidelines)

Bluetooth BPF Requirements

Harmonic	Center Frequency (MHz)	Min BPF Attenuation (dB)
Fundamental	2450	1.5
2	4900	26
3	7350	26
4	9800	19
5	12250	12
6	14700	9

1. Is there an option to perform conducted testing(U.FL Coaxial Test Port) for RF Testing?
2. Is matching circuit in place for antenna support?

All Other Pins

1. Leave NC - Do not use for any other routing purposes

---

CC256x PCB Layout Checklist

This section will describe the PCB guidelines in a checklist format to speed up the PCB design using the CC256x QFN device by checking this list. This will ensure the design will pass BT SIG certification and also minimize risk for regulatory certifications including FCC, ETSI, and CE.

Note: It is mandatory to copy/paste the reference design area from our EM board to reuse our certification.

General Guidelines

1. Did you verify the recommended PCB stack up in the PCB Design guidelines?
2. Did you verify the dimensions of the QFN PCB footprint in section 5 of PCB Design Guidelines and Section 6 in the DS?
3. Are decoupling capacitors as close as possible to QFN device?

Power Supply

• Power

1. Is the trace width is at least 10 mils for the VBAT and VIO traces?
2. Are length of traces as short as possible (pin to pin)?
3. Are decoupling caps close to QFN device as possible:
   1. Is MLDO_IN cap close to pin B5?
   2. Is VDD_IO cap close to pins B18 and A17?

• LDOs

1. Is trace width for the trace between x_LDO_x pins and decoupling caps at least 5 mils (recommend 10 mils where possible)?
2. Is the decoupling capacitor of MLDO_OUT (C20) as close as possible to pin A5?
3. Are these caps close to these pins:
   1. Is DIG_LDO_OUT_ Cap close to ball B15?
   2. Is DIG_LDO_OUT_ Cap close to ball B27?
   3. Is DIG_LDO_OUT_ Cap close to ball B36?
4. Is the cap for DIG_LDO_OUT connected to ball B36 isolated from the top layer GND (See PCB DG Sec. 3.2)?
5. Are the decoupling caps for SRAM, ADCPPA and CL1.5 LDO_OUT close as possible to their corresponding pins on CC256x?
6. Is the device and the capacitors together on the top side?
7. Is each capacitor's ground connection directly connected to solid ground layer (layer 2)?
8. Is capacitor directly connected to pin A12 (DCO_LDO_OUT) close to device?
9. Is DCO_LDO_OUT capacitor isolated from layer 1 ground and connected directly to layer 2 solid ground?

• Ground

1. Is layer 2 solid ground plane?
2. Is VSS_FREF isolated from GND on top layer and routed directly to GND on 2nd layer? (See PCB DG section 4.5.1)
3. Is VSS_DCO (B11 Ball) isolated from GND? Illustrated as part of the DCO_LDO_OUT cap? (See section 3.3 in PCB DG)
4. Is there at least 13 vias on the thermal pad to increase ground coupling?
5. Is VSS_FREF(B3) not connected to thermal pad (instead connected directly to solid ground)?

User Interfaces

• UART

1. Is the UART trace width at least 5 mils?
2. Are the 4 UART lines run as a bus interface?
3. Are clocks, DC supply or RF traces NOT near these UART traces?
4. Is the GND plane on layer 2 is solid below these lines and there is ground around these traces on top layer?

• PCM

1. Is the trace width at least 5 mils?
2. Are the four PCM lines run as a bus interface and roughly the same length?
3. Are clocks, DC supply, RF traces, and LDO caps are NOT near these PCM traces?
4. Is the GND plane on layer 2 is solid below these lines and there is ground around these traces on top layer?

• TX_DBG

1. Is there an accessible test point on the board from TX_DBG pin B24?

Clock Interfaces

• Slow Clock

1. Is the slow clock trace width at least 5 mils?
2. Are the slow clock signal lines as short as possible?
3. Is the GND plane on layer 2 is solid below these lines and there is ground around these traces on top layer?

• Fast Clock

1. Is the fast clock trace width at least 5 mils?
2. Are crystal tuning caps close to crystal pads?
3. Are both traces(XTALM and XTALP) in parallel as much as possible and roughly the same length?
4. Is the GND plane on layer 2 solid below these lines and there is ground around these traces on top layer?

RF Interface

1. Is there an RF shield (recommended, not mandatory)?
2. Is RF traces routed on the top layer and matched at 50-Ω with reference to ground?
3. Is the RF line routed between these NC pins: NC_2 (A10), NC_3 (A11),NC_14 (B9), NC_15 (B10), which are grounded for better RF isolation?

• These pins are NC at the chip level but it is recommended to ground them on the PCB layout for better RF isolation.

1. Is the area underneath the BPF pads grounded on layer 1 and 2?
2. Is the RF_IN and RF_OUT of the BPF pads kept clear of any ground fill? (See Sect. 4.1.1 PCB DG)
3. Follow guidelines specified in the vendor specific antenna design guides (including placement of antenna)?
4. Follow guidelines specified in the vendor specific BPF design guides?
5. Is the Bluetooth RF trace a 50-Ω, impedance-controlled trace with reference to solid ground?
6. Is the RF trace length as short as possible?

Related Documents

• CC256X QFN PCB Guidelines
• CC256x QFN Reference Design
• CC256x Datasheet