CC256x Fast Clock Information

Today is Tuesday 1 December 2020

NOTE: This wiki is under development and shall not be used as a reference at this moment. Thank you for your understanding.

AC-Coupled External Fast Clock Source

When using an external sinusoidal fast clock source, the XTALM (or FREFM) is tied to VDD_IO, and the XTALP (or FREFP) is through a DC block capacitor connected the clock source (Figure 1). The sinusoidal amplitude needs to be between 0.4 and 1.6 Vp-p (Figure 2).

In cases where the input amplitude is greater than 1.6 Vp-p, the amplitude can be reduced to within the limits shown by using a small series capacitor. This forms a voltage divider with the internal ~2 pF input capacitance to provide the required amplitude at the CC256x input pin.

Supported external clock source rates are 19.2, 26 and 38.4 MHz. The fast clock accuracy must not exceed ±20 ppm (as per Bluetooth specification).


Figure 1: AC-coupled external sinusoidal fast clock source.


Figure 2: Range of required sinusoidal fast clock amplitude.

DC-Coupled External Fast Clock Source

When using an external DC-coupled clock source, the XTALP (or FREFP) is tied to GND, and the XTALM (or FREFM) is directly connected to the clock source (Figure 3).

If a square wave is being used the low square wave level must be between -0.2V and 0.37V, while the high level must be between 1.0V and 2.1V (Figure 4).

If a sinusoidal clock signal is being used, the clock amplitude must be between 0.4Vpp and 1.6Vpp with a DC offset level between 0.2VDC and 1.4VDC (Figure 5).

Supported external clock source rates are 19.2, 26 and 38.4 MHz. The fast clock accuracy must not exceed ±20 ppm (as per Bluetooth specification).

Figure 3: DC-coupled external squarewave fast clock source.


Figure 4: Range of required DC-coupled squarewave fast clock amplitude.


Figure 5: Range of required DC-coupled sinusoidal fast clock amplitude.

XTALP and XTALM input impedances

The equivalent port impedance of the XTALP and XTALM ports when configured for external sinusoidal or squarewave fast clock signals is listed in Figure 6. The port's equivalent circuit of Rp and Cp is shown in Figure 7.


Figure 6: The equivalent port impedance of XTALP and XTALM.


Figure 7: The equivalent circuit of XTALP and XTALM input ports.

Use of External Crystal

The external crystal is connected to the XTALM (FREFM) and XTALP (FREFP) is appropriate capacitance loading to ground on each pin (Figure 8). The typical capacitive loading is between 8 and 20 pF, depending on the crystal manufacturer’s datasheet.

To ensure proper oscillation, the ESR of the crystal should be about 25% of the CC256x/BL6450L’s datasheet value for the crystal oscillator’s negative resistance (SWRS098B), (Figure 9). As an example of a 26 MHz crystal with 12 pF capacitive loading to GND, the crystal’s ESR should be around 0.25*580 Ω= 145 Ω.

Supported external crystal frequencies are 26 and 38.4 MHz (19.2 MHz is not supported). The fast clock accuracy must not exceed ±20 ppm (as per Bluetooth specification).


Figure 8: Use of external crystal.


Figure 9: Fast clock requirements.

CLK_REQ_OUT Output Pin

This is an output from the CC256x/BL6450L that is being used when an external fast clock source is to be enabled/disabled to save power during sleep cycles. It is a 1.8V digital output signal.

A 82 kΩ pulldown resistor is needed on this pin when used as an external fast clock source’s enable/disable function.

If the CLK_REQ_OUT is not used, tie directly to VIO.

The CLK_REQ_OUT pin has the following characteristics when in use:

• CC256x/BL6450L device is shut down: High-Z
  
• CC256x/BL6450L device is active: Low level (i.e. ext. clock source enabled)
  
• CC256x/BL6450L device is deep sleep: High level (i.e. ext. clock source disabled)