C674x crystal and pll frequencies

What frequency crystal should I use if I want to get the most CPU horsepower from the C674x?

If you're trying to save money or board space and reduce the number of crystals in a design, you need to pay attention to all the frequency requirements of all the peripherals. The USB and Ethernet MAC are of particular interest, but there may be others.

The data sheet was updated recently (9/1/2010), and things have changed a bit. The max clock frequency was changed from 300 MHz to either 375 or 456 MHz. The previous specification said that the minimum PLLOUT was 400 MHz, and thus you had to use POSTDIV /2 to get to 300 MHz. However, now PLLOUT was updated to a minimum of 300 MHz to a maximum of 600 MHz. This implies that POSTDIV must == 1 to get to either 375 or 456 MHz CPU clock.

This means that at 375 MHz speed bin, there is no longer a single-crystal solution that will work to get maximum CPU clock speed, and USB compatability. USB requires a crystal at one of these fixed frequencies: 12, 24, 48, 19.2, 38.4, 13, 26, 20, or 40 MHz. None of the factors of 375 (1 3 5 15 25 75 125) overlap with any of the USB frequencies.

However, for the 456 MHz speed bin, a 24 MHz crystal will work for USB & CPU maximum.

If you can afford to give up 15 MHz on the 375 MHz design, you can design with a 24 MHz crystal, and get USB and hit 300, 360 and 456 MHz.

Notes

Use a crystal between 18.75 MHz and 30 MHz.

For 375 MHz

• 25 MHz with PLLDIV=1, PLLM=14 ( PLL_CLKOUT = 25 MHz * (14+1)= 375 MHz <-- okay for ethernet, but not really.
• 24 MHz with PLLDIV=1, PLLM=14 ( PLL_CLKOUT = 24 MHz * (14+1)= 360 MHz <-- okay for USB
• 20 Mhz with PLLDIV=1, PLLM=19 ( PLL_CLKOUT = 20 MHz * (20+1)= 360 MHz <-- okay for USB

For 456 MHz

• 25 MHz with PLLDIV=1, PLLM=17 ( PLL_CLKOUT = 25 MHz * (17+1)= 450 MHz <-- okay for ethernet, but not really.
• 24 MHz with PLLDIV=1, PLLM=18 ( PLL_CLKOUT = 24 MHz * (18+1)= 456 MHz <-- okay for USB
• 20 Mhz with PLLDIV=1, PLLM=21 ( PLL_CLKOUT = 20 MHz * (21+1)= 440 MHz <-- okay for USB

1. This set of frequencies does not allow for a perfect audio sample rate for any of the normal sample rates. You must either use an external MCLK, or a codec with its own PLL.
2. If you're trying to use the ethernet EMAC, you'll want to use an external 50 MHz reference clock, and not one generated on-chip. This is because (as noted in SPRUFK4D), "The SYSCLK7 output clock does not meet the RMII reference clock specification of 50MHz +/-50ppm."
3. If you want to use USB, and you are not using the USB_REFCLKIN, then the PLL clock comes from AUXCLK. AUXCLK is the same frequency as your crystal frequency. And SPRUFK4D states that, "PLL0_AUXCLK must be 12, 24, 48, 19.2, 38.4, 13, 26, 20, or 40 MHz." This means that for full 300 MHz clocking and USB, you must use a 20 or 24 MHz crystal.

There is no crystal that will work for USB+Ethernet. But, you don't want to use the internal oscillator for ethernet anyway.

Okay, so, to get the 600 MHz PLL_CLKOUT, you can use a crystal as high as 30 MHz, with a pll multiplier value of 20 (PLLM=19). The smallest frequency crystal you can use is actually determined by the maximum pll multiplier of 32 (PLLM=31). So, the lowest frequency crystal is: 600/32 = 18.75 MHz.