C64x+

Important Note:

This wiki is in maintenance mode and the information on this wiki may not be current. The device architecture is supported on C6000 DSP E2E forum

The C64x+ core design from TI is a highly parallel DSP core that is based upon it's predecessor, the c64 core. It is the basis for many of the DaVinci, OMAP and C6000 High Performance DSP devices.

Support for DDR and SDRAM memories on the C64x+ platform.

The C64x+ core devices are the first C6000 DSP devices to support DDR memory. These devices have a dedicated EMIF peripheral for supporting DDR memories. Please note that the devices that will support DDR are not going to support SDRAM.

Devices supporting DDR memory: C645x and future C64x+ core devices.

Devices supporting SDRAM memory: All C641x devices.

What is the maximum data rate that the C64x+ EMIF supports with DDR?

The C64x+ devices supports DDR data rates of up to 2 GB per second. This is achieved with a dedicated PLL that will generate a 250 MHz clock for the DDR memory. With the double data rate capability, a 250 MHz clock translates to 500 million words per second. Since the DDR data bus is 32 bits wide, this translates to 500 million 32-bit words, or 2 GB per second of total data throughput on the DDR interface.

How to process floating-point data on DM6446 from the DSP side?

DM6446 has a C64x+ DSP core. However, this DSP core does not support floating point operations in hardware;floating point operations on this platform will take place in software such as a C program. The standard run time support library will allow you to do floating point operations in C code as it is, though if you are looking for additional performance beyond the standard RTS there is an IQMath library for the C64x+ available that may be of some help.